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| this is information on a product in full production. june 2012 doc id 023331 rev 1 1/102 1 stm8l052c6 value line, 8-bit ultralow power mcu, 32-kb flash, 256-byte data eeprom, rtc, lcd, timers, usart, i2c, spi, adc datasheet ? production data features operating conditions ? operating power supply: 1.8 v to 3.6 v ? temperature range: -40 c to 85 c low power features ? 5 low power modes: wait, low power run (5.1 a), low power wait (3 a), active-halt with full rtc (1.3 a), halt (350 na) ? consumption: 195 a/mhz + 440 a ? ultra-low leakage per i/0: 50 na ? fast wakeup from halt: 4.7 s advanced stm8 core ? harvard architecture and 3-stage pipeline ? max freq. 16 mhz, 16 cisc mips peak ? up to 40 external interrupt sources reset and supply management ? low power, ultra-safe bor reset with 5 selectable thresholds ? ultra low power por/pdr ? programmable voltage detector (pvd) clock management ? 32 khz and 1 to 16 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc ? internal 38 khz low consumption rc ? clock security system low power rtc ? bcd calendar with alarm interrupt ? auto-wakeup from halt w/ periodic interrupt lcd: up to 4x28 segments w/ step-up converter memories ? 32 kb flash program memory and 256 bytes data eeprom with ecc, rww ? flexible write and read protection modes ? 2 kbytes of ram dma ? 4 channels supporting adc, spi, i2c, usart, timers ? 1 channel for memory-to-memory 12-bit adc up to 1 msps/25 channels ? internal reference voltage timers ? two 16-bit timers with 2 channels (used as ic, oc, pwm), quadrature encoder ? one 16-bit advanced control timer with 3 channels, supporting motor control ? one 8-bit timer with 7-bit prescaler ? 2 watchdogs: 1 window, 1 independent ? beeper timer with 1, 2 or 4 khz frequencies communication interfaces ? synchronous serial interface (spi) ?fast i 2 c 400 khz smbus and pmbus ? usart (iso 7816 interface and irda) up to 41 i/os, all mappab le on interrupt vectors development support ? fast on-chip programming and non- intrusive debugging with swim ? bootloader using usart lqfp48 www.st.com
contents stm8l052c6 2/102 doc id 023331 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 ultra low power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 advanced stm8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.1 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10 system configuration controller and routi ng interface . . . . . . . . . . . . . . . 19 3.11 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.1 tim1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.2 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.3 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.1 window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12.2 independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.2 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 stm8l052c6 contents doc id 023331 rev 1 3/102 3.14.3 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 system configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.2 embedded reset and power control block characteristics . . . . . . . . . . . 56 8.3.3 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.3.4 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.3.6 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.3.7 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.3.8 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3.9 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.3.10 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.11 12-bit adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.3.12 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 contents stm8l052c6 4/102 doc id 023331 rev 1 9 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.1 ecopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.2.1 48-pin low profile quad flat 7x7mm package (lqfp48) . . . . . . . . . . . . . 98 10 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 stm8l052c6 list of tables doc id 023331 rev 1 5/102 list of tables table 1. medium density value line stm8l 05xxx low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3. legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 4. medium density value line stm8l05xxx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 9. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 10. option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 11. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 12. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 13. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 14. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 15. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. total current consumption in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 18. total current consumption in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 19. total current consumption and timing in low power run mode at vdd = 1.8 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 20. total current consumption in low power wait mode at vdd = 1.8 v to 3.6 v . . . . . . . . . . 63 table 21. total current consumption and timing in ac tive-halt mode at vdd = 1.8 v to 3.6 v. . . . . . 64 table 22. typical current consumption in active-halt mode, rtc clocked by lse external crystal . . 65 table 23. total current consumption and timing in halt mode at vdd = 1.8 to 3.6 v . . . . . . . . . . . . 65 table 24. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 25. current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 26. hse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 27. lse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 28. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 29. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 30. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 31. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 32. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 33. flash program and da ta eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 34. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 35. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 36. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 37. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 38. output driving current (pa0 wi th high sink led driver capability). . . . . . . . . . . . . . . . . . . . 77 table 39. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 40. spi1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 41. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 42. lcd characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 43. reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 44. adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 45. adc1 accuracy with vdda = 3.3 v to 2.5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 46. adc1 accuracy with vdda = 2.4 v to 3.6 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 list of tables stm8l052c6 6/102 doc id 023331 rev 1 table 47. adc1 accuracy with vdda = vref + = 1.8 v to 2.4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 48. r ain max for f adc = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 49. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 50. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 51. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 52. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 53. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 54. lqfp48 48-pin low profile quad flat package, mechanical data. . . . . . . . . . . . . . . . . . . . . 98 table 55. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 stm8l052c6 list of figures doc id 023331 rev 1 7/102 list of figures figure 1. medium density value line stm8l05xxx device block diagram . . . . . . . . . . . . . . . . . . . . 12 figure 2. medium density value line stm8l05xxx clock tree di agram . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. stm8l052c6 48-pin lqfp48 package pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 6. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 7. por/bor thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 8. typ. idd(run) vs. vdd, fcpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 9. typ. idd(wait) vs. vdd, fcpu = 16 mhz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 10. typ. idd(lpr) vs. vdd (lsi clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. typ. idd(lpw) vs. vdd (lsi clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 12. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 13. lse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 14. typical hsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 15. typical lsi frequency vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 16. typical vil and vih vs vdd (high sink i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 17. typical vil and vih vs vdd (true open drain i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 18. typical pull-up resistance r pu vs v dd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 19. typical pull-up current i pu vs v dd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 20. typ. vol @ vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 21. typ. vol @ vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 22. typ. vol @ vdd = 3.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 23. typ. vol @ vdd = 1.8 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 24. typ. vdd - voh @ vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 25. typ. vdd - voh @ vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 26. typical nrst pull-up resistance r pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 27. typical nrst pull-up current i pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 28. recommended nrst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 29. spi1 timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 30. spi1 timing diagram - slave mode and cpha=1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 31. spi1 timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 32. typical application with i2c bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 33. adc1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 34. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 35. maximum dynamic current consumption on v ref+ supply pin during adc conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 36. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 93 figure 37. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . . 93 figure 38. lqfp48 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 39. lqfp48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 40. medium density value line stm8l05xxx ordering information scheme . . . . . . . . . . . . . . 100 introduction stm8l052c6 8/102 doc id 023331 rev 1 1 introduction this document describes the features, pinout, mechanical data and ordering information of the medium density value line stm8l052c6 microcontroller with 32-kbyte flash memory density. for further details on the whole stmicroelectronics medium density family please refer to section 2.2: ultra low power continuum . for detailed information on device operation and registers, refer to the reference manual (rm0031). for information on to the flash program memory and data eeprom, refer to the programming manual (pm0054). for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, refer to the stm8 cpu programming manual (pm0044). medium density value line devices provide the following benefits: integrated system ? 32 kbytes of medium density embedded flash program memory ? 256 bytes of data eeprom ? 2 kbytes of ram ? internal high speed and low-power low speed rc ? embedded reset ultra low power consumption ? 195 a/mhz + 440 a (consumption) ? 0.9 a with lsi in active-halt mode ? clock gated system and optimized power management ? capability to execute from ram for low power wait mode and low power run mode advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? direct memory access (dma) for memory-to-memory or peripheral-to-memory access short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals ? wide choice of development tools refer to table 1: medium density value line stm8l05xxx low power device features and peripheral counts and section 3: functional overview for an overview of the complete range of peripherals proposed in this family. figure 1 shows the block diagram of the medium density value line stm8l05xxx family. stm8l052c6 description doc id 023331 rev 1 9/102 2 description the medium density value line stm8l05xxx devices are members of the stm8l ultra low power 8-bit family. the value line stm8l05xxx ultra low power fam ily features the enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. the family includes an integrated debug module with a hardware interface (swim) which allows non-intrusive in-application debug ging and ultra-fast flash programming. medium density value line stm8l05xxx microc ontrollers feature em bedded data eeprom and low-power, low-voltage, single-supply program flash memory. all devices offer 12-bit adc, real-time clock, 16-bit timers, one 8-bit timer as well as standard communication interface such as spi, i2c, usart and 4x28-segment lcd. the 4x 28-segment lcd is available on the medium density value line stm8l05xxx. the stm8l05xxx family operates from 1.8 v to 3.6 v and is available in the - 40 to +85 c temperature range. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families includ ing 32-bit families. this make s any transition to a different family very easy, and simplified even more by the use of a common set of development tools. all value line stm8l ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout. description stm8l052c6 10/102 doc id 023331 rev 1 2.1 device overview table 1. medium density value line stm8l05xxx low power device features and peripheral counts features stm8l052c6 flash (kbytes) 32 data eeprom (bytes) 256 ram (kbytes) 2 lcd 4x28 timers basic 1 (8-bit) general purpose 2 (16-bit) advanced control 1 (16-bit) communication interfaces spi 1 i2c 1 usart 1 gpios 41 (1) 1. the number of gpios given in this table includes the nrst/pa1 pin but the application can use the nrst/pa1 pin as general purpose output only (pa1). 12-bit synchronized adc (number of channels) 1 (25) others rtc, window watchdog, independent watchdog, 16-mhz and 38-khz internal rc, 1- to 16-mhz and 32-khz external oscillator cpu frequency 16 mhz operating voltage 1.8 v to 3.6 v operating temperature -40 to +85 c package lqfp48 stm8l052c6 description doc id 023331 rev 1 11/102 2.2 ultra low power continuum the ultra low power value line stm8l05xxx and stm8l15xxx are fully pin-to-pin, software and feature compatible. besides the full comp atibility within the stm8l family, the devices are part of stmicroelectronics microcontrollers ul tra low power strategy which also includes stm8l101xx and stm32 l15xxx. the stm8l and stm32l families allow a continuum of performance, peripherals, system architecture, and features. they are all based on stmicroelectronics 0.13 m ultra-low leakage process. note: 1 the stm8l05xxx is pin-to-pin compatible with stm8l101xx devices. 2 the stm32l family is pin-to-pin compatible with the general purpose stm32f family. please refer to stm32l15x documentation for more information on these devices. performance all families incorporate highly energy-efficien t cores with both harvar d architecture and pipelined execution: advanced stm8 core fo r stm8l families and arm cortex?-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultra low power performance to range from 5 up to 33.3 dmips. shared peripherals stm8l05x, stm8l15x and stm32l15xx share identical peripherals which ensure a very easy migration from one family to another: analog peripheral: adc1 digital peripherals: rtc and some communication interfaces common system strategy to offer flexibility and opti mize performance, the stm8 l and stm32l devices use a common architecture: same power supply range from 1.8 to 3.6 v architecture optimized to reach ultra-low consumption both in low power modes and run mode fast startup strategy from low power modes flexible system clock ultra-safe reset: same reset strategy for both stm8l and stm32l including power-on reset, power-down reset, brownout reset and programmable voltage detector features st ultra low power continuum al so lies in feature compatibility: more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm memory density ranging from 4 to 128 kbytes functional overview stm8l052c6 12/102 doc id 023331 rev 1 3 functional overview figure 1. medium density value line stm8l05xxx device block diagram 1. legend : adc: analog-to-digital converter bor: brownout reset dma: direct memory access i2c: inter-integrated circuit multimaster interface lcd: liquid crystal display por/pdr: power on reset / power down reset rtc: real-time clock spi: serial peripheral interface swim: single wire interface module usart: universal synchronous asyn chronous receiver transmitter wwdg: window watchdog iwdg: independent watchdog 16 mhz internal rc clock clocks address, control and data buses debug module spi1 32 kbytes interrupt controller 2 kbytes ram to core and peripherals iwdg (38 khz clock) (swim) port a port b port c i2c1 usart1 power volt. reg. port f 1-16 mhz oscillator 32 khz oscillator 38 khz internal rc lcd driver 4x28 wwdg stm8 core controller and css 256 bytes port d port e beeper rtc memory program data eeprom @v dd v dd18 v dd1 =1.8 v v ss1 swim scl, sda, mosi, miso, sck, nss rx, tx, ck adc1_inx v dda v ssa smb @v dda /v ssa 12-bit adc1 v ref+ v ref- 3.6 v nrst pa[7:0] pb[7:0] pc[7:0] pd[7:0] pe[7:0] pf0 beep alarm, calib segx, comx por/pdr osc_in, osc_out osc32_in, osc32_out to bor pvd pvd_in reset dma1 8-bit timer 4 16-bit timer 3 16-bit timer 2 16-bit timer 1 (4 channels) 2 channels 2 channels 3 channels v lcd = 2.5 v 3.6 v to lcd booster internal reference voltage vrefint out infrared interface ir_tim stm8l052c6 functional overview doc id 023331 rev 1 13/102 3.1 low power modes the medium density value line stm8l05xxx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: wait mode : the cpu clock is stopped, but selected peripherals keep running. an internal or external interrupt, event or a reset can be used to exit the microcontroller from wait mode (wfe or wfi mode). low power run mode : the cpu and the selected peripherals are running. execution is done from ram with a low speed oscilla tor (lsi or lse). fl ash memory and data eeprom are stopped and the vo ltage regulator is configur ed in ultra low power mode. the microcontroller enters low power run mode by software and can exit from this mode by software or by a reset. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power wait mode: this mode is entered when executing a wait for event in low power run mode. it is similar to low power run mode except that the cpu clock is stopped. the wakeup from this mode is triggered by a reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, dma controller (dma1) and i/o ports). when the wakeup is triggered by an event, the system goes back to low power run mode. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. active-halt mode : cpu and peripheral clocks are stopped, except rtc. the wakeup can be triggered by rtc interrupts, external interrupts or reset. halt mode : cpu and peripheral clocks are stopped, the device remains powered on. the ram content is preserved. the wakeup is triggered by an external interrupt or reset. a few peripherals have also a wake up from halt capability. switching off the internal reference voltage reduces power consumption. through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 s. functional overview stm8l052c6 14/102 doc id 023331 rev 1 3.2 central processing unit stm8 3.2.1 advanced stm8 core the 8-bit stm8 core is designed for code efficiency and performance with an harvard architecture and a 3-stage pipeline. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus - si ngle cycle fetching most instructions x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-mbyte linear memory space 16-bit stack pointer - access to a 64-kbyte level stack 8-bit condition code register - 7 condition flags for the result of the last instruction addressing 20 addressing modes indexed indirect addressing mode for lookup tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers 3.2.2 interrupt controller the medium density value line stm8l05xxx devices feature a nested vectored interrupt controller: nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority up to 40 external interrupt sources on 11 vectors trap and reset interrupts stm8l052c6 functional overview doc id 023331 rev 1 15/102 3.3 reset and supply management 3.3.1 power supply scheme the device requires a 1.8 v to 3.6 v operating supply voltage (v dd ). the external power supply pins must be connected as follows: v ss1 ; v dd1 = 1.8 to 3.6 v: external power supply for i/os and for the internal regulator. provided externally through v dd1 pins, the corresponding ground pin is v ss1 . v ssa ; v dda = 1.8 to 3.6 v: external power supplies for analog peripherals. v dda and v ssa must be connected to v dd1 and v ss1 , respectively. v ss2 ; v dd2 = 1.8 to 3.6 v: external power supplies for i/os. v dd2 and v ss2 must be connected to v dd1 and v ss1 , respectively. v ref+ ; v ref- (for adc1): external reference voltage for adc1. must be provided externally through v ref+ and v ref- pin. 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr), coupled with a brownout reset (bor) circuitry . at power-on, bor is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently. five bor thresholds are available through option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the bor) in halt mode. the device remains under reset when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the medium density value line stm8l05xxx embeds an internal voltage regulator for generating the 1.8 v power supply for the core and peripherals. this regulator has two different modes: main voltage regulator mode (mv r) for run, wait for interrupt (wfi) and wait for event (wfe) modes low power voltage regulator mode (lpvr) for halt, active-halt, low power run and low power wait modes when entering halt or active-halt modes, the system automatically switches from the mvr to the lpvr in order to reduce current consumption. functional overview stm8l052c6 16/102 doc id 023331 rev 1 3.4 clock management the clock controller distributes the system clock (sysclk) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cp u and peripherals can be adjusted by a programmable prescaler. safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. system clock sources: 4 different clock sources can be used to drive the system clock: ? 1-16 mhz high speed external crystal (hse) ? 16 mhz high speed internal rc oscillator (hsi) ? 32.768 khz low speed external crystal (lse) ? 38 khz low speed internal rc (lsi) rtc and lcd clock sources: the above four sources can be chosen to clock the rtc and the lcd, whatever the system clock. startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the system clock is automatically switched to hsi. configurable main clock output (cco): this outputs an external clock for use by the application. stm8l052c6 functional overview doc id 023331 rev 1 17/102 figure 2. medium density value line stm8l05xxx clock tree diagram 1. the hse clock source can be either an external crystal/ceramic res onator or an external source (hse bypass). refer to section hse clock in the stm8l15x and stm8l16x reference manual (rm0031). 2. the lse clock source can be either an external crystal/ceramic resonat or or a external source (lse bypass). refer to section lse clock in the stm8l15x and stm8l16x reference manual (rm0031). 3.5 low power real-time clock the real-time clock (rtc) is an independent binary coded decimal (bcd) timer/counter. six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day months are made automatically. it provides a programmable alarm and programmable periodic interrupts with wakeup from halt capability. periodic wakeup time using the 32.768 khz lse with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. with a different resolution, the wakeup time can reach 36 hours. periodic alarms based on the calendar can also be generated from every second to every year. hse osc 1-16 mhz hsi rc 16 mhz lsi rc 38 k hz lse osc 32 768 k h z hsi lsi rtc prescaler /1;2;4;8;16;32;64 pclk to peripherals rtcclk/2 to lcd to iwdg sysclk hse (1) (2) lsi lse osc_out osc32_out osc_in osc32_in clock output cco prescaler /1;2;4;8;16;32;64 hsi lsi hse lse cco to core and memory sysclk prescaler /1;2;4;8;16;32;64;128 iwdgclk rtcsel[3:0] lse (2) clkbeepsel[1:0] to beep beepclk css configurable . / 2 peripheral clock enable (15 bits) to rtc rtcclk clock enable (1 bit) lcdclk to lcd sysclk halt clock enable (1 bit) lcd peripheral rtcclk lcd peripheral (1) (2) functional overview stm8l052c6 18/102 doc id 023331 rev 1 3.6 lcd (liquid crystal display) the lcd is only availabl e on stm8l052xx devices. the liquid crystal display drives up to 4 common terminals and up to 28 segment terminals to drive up to 112 pixels. internal step-up converter to guarantee contrast control whatever v dd . static 1/2, 1/3, 1/4 duty supported. static 1/2, 1/3, bias supported. phase inversion to reduce power consumption and emi. up to 4 pixels which ca n be programmed to blink. the lcd controller can operate in halt mode. note: unnecessary segments and common pins can be used as general i/o pins. 3.7 memories the medium density value line stm8l05xxx devices have the following main features: 2 kbytes of ram the non-volatile memory is divided into three arrays: ? 32 kbytes of medium density embedded flash program memory ? 256 bytes of data eeprom ?option bytes the eeprom embeds the error correction code (e cc) feature. it supp orts the read-while- write (rww): it is possible to execute the code from the program matrix while programming/erasing the data matrix. the option byte protects part of the flash program memory from write and readout piracy. 3.8 dma a 4-channel direct memory access controlle r (dma1) offers a memory-to-memory and peripherals-from/to-memory tr ansfer capability. the 4 chann els are shared between the following ips with dma capability: adc1, i2 c1, spi1, usart1and the four timers. stm8l052c6 functional overview doc id 023331 rev 1 19/102 3.9 analog-to-digital converter 12-bit analog-to-digital converter (adc1) with 25 channels (including 1 fast channel) and internal reference voltage conversion time down to 1 s with f sysclk = 16 mhz programmable resolution programmable sampling time single and continuous mode of conversion scan capability: automatic conversion perfor med on a selected gr oup of anal og inputs analog watchdog triggered by timer note: adc1 can be served by dma1. 3.10 system configuration cont roller and routing interface the system configuration controller provides the capability to remap some alternate functions on different i/o ports. tim4 and adc1 dma channels can also be remapped. the highly flexible routing interface allows application software to control the routing of different i/os to the tim1 timer input captures. it also controls the routing of internal analog signals to adc1 and the internal reference voltage v refint . 3.11 timers the medium density value line stm8l05xxx devices contain one advanced control timer (tim1), two 16-bit general purpose timers (tim2 and tim3) and one 8-bit basic timer (tim4). all the timers can be served by dma1. ta bl e 2 compares the features of the advanced control, general-purpose and basic timers. table 2. timer feature comparison timer counter resolution counter type prescaler factor dma1 request generation capture/compare channels complementary outputs tim1 16-bit up/down any integer from 1 to 65536 ye s 3 + 1 3 tim2 any power of 2 from 1 to 128 2 none tim3 tim4 8-bit up any power of 2 from 1 to 32768 0 functional overview stm8l052c6 20/102 doc id 023331 rev 1 3.11.1 tim1 - 16-bit ad vanced control timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver. 16-bit up, down and up/down autoreload counter with 16-bit prescaler 3 independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output 1 additional capture/compare channel which is not connected to an external i/o synchronization module to control the timer with external signals break input to force timer outputs into a defined state 3 complementary outputs with adjustable dead time encoder mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) 3.11.2 16-bit general purpose timers 16-bit autoreload (ar) up/down-counter 7-bit prescaler adjustable to fixed power of 2 ratios (1?128) 2 individually configurable capture/compare channels pwm mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.11.3 8-bit basic timer the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase generation with interrupt generation on timer overflow. 3.12 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. 3.12.1 window watchdog timer the window watchdog (wwdg) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.12.2 independent watchdog timer the independent watchdog peripheral (iwdg) can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the internal lsi rc clock source, and thus stays active even in case of a cpu clock failure. stm8l052c6 functional overview doc id 023331 rev 1 21/102 3.13 beeper the beeper functi on outputs a signal on the beep pin for sound gener ation. the signal is in the range of 1, 2 or 4 khz. 3.14 communication interfaces 3.14.1 spi the serial peripheral interface (spi1) provides half/ full duplex synchronous serial communication with external devices. maximum speed: 8 mbit/s (f sysclk /2) both for master and slave full duplex synchronous transfers simplex synchronous transfers on 2 lines with a possible bidirectional data line master or slave operation - selectable by hardware or software hardware crc calculation slave/master selection input pin note: spi1 can be served by the dma1 controller. 3.14.2 i2c the i 2 c bus interface (i 2 c1) provides multi-master capab ility, and controls all i2c bus- specific sequencing, protocol, arbitration and timing. master, slave and multi-master capability standard mode up to 100 khz and fast speed modes up to 400 khz 7-bit and 10-bit addressing modes smbus 2.0 and pmbus support hardware crc calculation note: i 2 c1 can be served by the dma1 controller. 3.14.3 usart the usart interface (usart1) allows full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. 1 mbit/s full duplex sci spi1 emulation high precision baud rate generator smartcard emulation irda sir encoder decoder single wire half duplex mode note: usart1 can be served by the dma1 controller. functional overview stm8l052c6 22/102 doc id 023331 rev 1 3.15 infrared (ir) interface the medium density value line stm8l05xxx device s contain an infrared interface which can be used with an ir led for remote control functions. two timer output compare channels are used to generate the infrared remote control signals. 3.16 development support development tools development tools for the stm8 microcontrollers include: the stice emulation system offe ring tracing and code profiling the stvd high-level language debugger including c compiler, assembler and integrated development environment the stvp flash programming software the stm8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. single wire data interface (swim) and debug module the debug module with its single wire data interface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single wire interface is used for direct access to the debugging module and memory programming. the interface can be activated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, cpu operation can also be monitored in real- time by means of shadow registers. bootloader a bootloader is available to reprogram the flash memory using the usart1 interface. the reference document for the bootloader is um0560: stm8 bootloader user manual . the bootloader is used to download application software into the device memories, including ram, program and data memory, using standard serial interfaces. it is a complementary solution to programming via the swim debugging interface. stm8l052c6 pin description doc id 023331 rev 1 23/102 4 pin description figure 3. stm8l052c6 48-pin lqfp48 package pinout (with lcd) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa5 v ss1 /v ssa/ v ref- nrst/pa1 pa2 pa3 pa4 pa6 vlcd pe0 pe1 pd1 pd2 pd3 pb0 pe3 pd0 pe5 pe4 pa7 v dd1 v dda v ref+ pe2 pb1 pb2 pc0 pc1 v dd2 v ss2 pc2 pc3 pc4 pc5 pc6 pc7 pe6 pe7 pb3 pb4 pb5 pb6 pb7 pf0 pd4 pd5 pd6 pd7 pa 0 pin description stm8l052c6 24/102 doc id 023331 rev 1 table 3. legend/abbreviation for table 4 type i= input, o = output, s = power supply level ft five-volt tolerant tt 3.6 v tolerant output hs = high sink/source (20 ma) port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state a fter reset release). unless otherwise specified, the pin state is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). table 4. medium density value line stm8l05xxx pin description pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 floating wpu ext. interrupt high sink/source od pp 2 nrst/pa1 (1) i/o x hs x reset pa 1 3 pa2/osc_in/ [usart1_tx] (8) / [spi1_miso] (8) i/o x x x hs x x port a2 hse oscillator input / [usart1 transmit] / [spi1 master in- slave out] 4 pa3/osc_out/ [usart1_ rx] (8) /[spi1_mosi] (8) i/o x x x hs x x port a3 hse oscillator output / [usart1 receive]/ [spi1 master out/slave in] / 5 pa4/tim2_bkin/ lcd_com0/adc1_in2 i/o tt (2) xxxhsxx port a4 timer 2 - break input / lcd com 0 / adc1 input 2 6 pa5/tim3_bkin/ lcd_com1/adc1_in1 i/o tt (2) xxxhsxx port a5 timer 3 - break input / lcd_com 1 / adc1 input 1 7 pa 6 / [adc1_trig] / lcd_com2/adc1_in0 i/o tt (2) xxxhsxx port a6 [adc1 - trigger] / lcd_com2 / adc1 input 0 8 pa7/lcd_seg0 (3) i/o ft x x x hs x x port a7 lcd segment 0 24 pb0 (4) /tim2_ch1/ lcd_seg10/adc1_in18 i/o tt (2) x (4) x (4) xhsx x port b0 timer 2 - channel 1 / lcd segment 10 / adc1_in18 25 pb1/tim3_ch1/ lcd_seg11/ adc1_in17 i/o tt (2) xxxhsxx port b1 timer 3 - channel 1 / lcd segment 11 / adc1_in17 26 pb2/ tim2_ch2/ lcd_seg12/ adc1_in16 i/o tt (2) xxxhsxx port b2 timer 2 - channel 2 / lcd segment 12 / adc1_in16 stm8l052c6 pin description doc id 023331 rev 1 25/102 27 pb3/tim2_etr/ lcd_seg13/ adc1_in15 i/o tt (2) xxxhsxx port b3 timer 2 - external trigger / lcd segment 13 /adc1_in15 28 pb4 (4) / [spi1_nss] (8) / lcd_seg14/ adc1_in14 i/o tt (2) x (4) x (4) xhsx x port b4 [spi1 master/slave select] / lcd segment 14 / adc1_in14 29 pb5/ [spi1_sck] (8) / lcd_seg15/ adc1_in13 i/o tt (2) xxxhsxx port b5 [spi1 clock] / lcd segment 15 / adc1_in13 30 pb6/[ spi1_mosi] (8) / lcd_seg16/ adc1_in12 i/o tt (2) xxxhsxx port b6 [spi1 master out/slave in] / lcd segment 16 / adc1_in12 31 pb7/ [spi1_miso] (8) / lcd_seg17/ adc1_in11 i/o tt (2) xxxhsxx port b7 [spi1 master in- slave out] /lcd segment 17 / adc1_in11 37 pc0 (3) /i2c1_sda i/o ft x x t (5) port c0 i2c1 data 38 pc1 (3) /i2c1_scl i/o ft x x t (5) port c1 i2c1 clock 41 pc2/usart1_rx/ lcd_seg22/adc1_in6/ vrefint i/o tt (2) xxxhsxx port c2 usart1 receive / lcd segment 22 / adc1_in6 /internal voltage reference output 42 pc3/usart1_tx/ lcd_seg23/ adc1_in5 i/o tt (2) xxxhsxx port c3 usart1 transmit / lcd segment 23 / adc1_in5 43 pc4/usart1_ck/ i2c1_smb/cco/ lcd_seg24/ adc1_in4 i/o tt (2) xxxhsxx port c4 usart1 synchronous clock / i2c1_smb / configurable clock output / lcd segment 24/ adc1_in4 44 pc5/osc32_in / [spi1_nss] (8) / [usart1_tx] (8) i/o x x x hs x x port c5 lse oscillator input / [spi1 master/slave select] / [usart1 transmit] 45 pc6/osc32_out/ [spi1_sck] (8) / [usart1_rx] (8) i/o x x x hs x x port c6 lse oscillator output / [spi1 clock] / [usart1 receive] 46 pc7/lcd_seg25/ adc1_in3 i/o tt (2) xxxhsxx port c7 lcd segment 25 /adc1_in3 table 4. medium density value line stm8l05xxx pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 floating wpu ext. interrupt high sink/source od pp pin description stm8l052c6 26/102 doc id 023331 rev 1 20 pd0/tim3_ch2/ [adc1_trig] (8) / lcd_seg7/adc1_in22/ i/o tt (2) xxxhsxx port d0 timer 3 - channel 2 / [adc1_trigger] / lcd segment 7 / adc1_in22 21 pd1/tim3_etr/ lcd_com3/ adc1_in21 i/o tt (2) xxxhsxx port d1 timer 3 - external trigger / lcd_com3 / adc1_in21 22 pd2/tim1_ch1 /lcd_seg8/ adc1_in20 i/o tt (2) xxxhsxx port d2 timer 1 - channel 1 / lcd segment 8 / adc1_in20 23 pd3/ tim1_etr/ lcd_seg9/adc1_in19 i/o tt (2) xxxhsxx port d3 timer 1 - externaltrigger / lcd segment 9 / adc1_in19 33 pd4/tim1_ch2 /lcd_seg18/ adc1_in10 i/o tt (2) xxxhsxx port d4 timer 1 - channel 2 / lcd segment 18 / adc1_in10 34 pd5/tim1_ch3 /lcd_seg19/ adc1_in9 i/o tt (2) xxxhsxx port d5 timer 1 - channel 3 / lcd segment 19 / adc1_in9 35 pd6/tim1_bkin /lcd_seg20/ adc1_in8/rtc_calib/ /vrefint i/o tt (2) xxxhsxx port d6 timer 1 - break input / lcd segment 20 / adc1_in8 / rtc calibration / internal voltage reference output 36 pd7/tim1_ch1n /lcd_seg21/ adc1_in7/rtc_alarm/v refint i/o tt (2) xxxhsxx port d7 timer 1 - inverted channel 1/ lcd segment 21 / adc1_in7 / rtc alarm / internal voltage reference output 14 pe0 (3) /lcd_seg1 i/o ft x x x hs x x port e0 lcd segment 1 15 pe1/tim1_ch2n/ lcd_seg2 i/o tt (2) xxxhsxx port e1 timer 1 - inverted channel 2 / lcd segment 2 16 pe2/tim1_ch3n/ lcd_seg3 i/o tt (2) xxxhsxx port e2 timer 1 - inverted channel 3 / lcd segment 3 17 pe3/lcd_seg4 i/o tt (2) xxxhsxx port e3 lcd segment 4 18 pe4/lcd_seg5 i/o tt (2) xxxhsxx port e4 lcd segment 5 19 pe5/lcd_seg6/ adc1_in23 i/o tt (2) xxxhsxx port e5 lcd segment 6 / adc1_in23 47 pe6/lcd_seg26/ pvd_in i/o tt (2) xxxhsxx port e6 lcd segment 26/pvd_in table 4. medium density value line stm8l05xxx pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 floating wpu ext. interrupt high sink/source od pp stm8l052c6 pin description doc id 023331 rev 1 27/102 note: the slope control of all gpio pins, except true open drain pins, can be programmed. by default, the slope control is limited to 2 mhz. 48 pe7/lcd_seg27 i/o tt (2) xxxhsxx port e7 lcd segment 27 32 pf0/adc1_in24 i/o x x x hs x x port f0 adc1_in24 13 vlcd s lcd booster external capacitor 13 reserved reserved. must be tied to v dd 10 v dd s digital power supply 11 v dda s analog supply voltage 12 v ref+ s adc1 positive voltage reference 9v ss1 /v ssa/ v ref- s i/o ground / analog ground voltage / adc1 negative voltage reference 39 v dd2 s ios supply voltage 40 v ss2 s ios ground voltage 1 pa 0 (6) / [usart1_ck] (8) / swim/beep/ir_tim (7) i/o x x (6) x hs (7) xx port a0 [usart1 synchronous clock] (8) / swim input and output /beep output / infrared timer output 1. at power-up, the pa1/nrst pin is a reset input pin with pull-up. to be used as a general purpose pin (pa1), it can be configured only as output open-drai n or push-pull, not as a general purpose input. refer to section configuring nrst/pa1 pin as general purpose output in the stm8l15x and stm8l16x reference manual (rm0031). 2. in the 3.6 v tolerant i/os, protection diode to v dd is not implemented. 3. in the 5 v tolerant i/os, protection diode to v dd is not implemented. 4. a pull-up is applied to pb0 and pb4 during the reset phase . these two pins are input floating after reset release. 5. in the open-drain output column, ?t? de fines a true open-drain i/o (p -buffer, weak pull-up and protection diode to v dd are not implemented). 6. the pa0 pin is in input pull-up during the reset phase and after reset release. 7. high sink led driver capability available on pa0. 8. [ ] alternate function remapping option (if the same alternate func tion is shown twice, it indi cates an exclusive choice not aduplication of the function). table 4. medium density value line stm8l05xxx pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 floating wpu ext. interrupt high sink/source od pp pin description stm8l052c6 28/102 doc id 023331 rev 1 4.1 system configuration options as shown in table 4: medium density value line stm8l05xxx pin description , some alternate functions can be remapped on different i/o ports by programming one of the two remapping registers described in the ? routing interface (ri) and system configuration controller? section in the stm8l15x and stm8l16x reference manual (rm0031). stm8l052c6 memory and register map doc id 023331 rev 1 29/102 5 memory and register map 5.1 memory mapping the memory map is shown in figure 4 . figure 4. memory map 1. table 5 lists the boundary addresses for each memory si ze. the top of the stack is at the ram end address. 2. refer to table 7 for an overview of hardware register mapping, to table 6 for details on i/o port hardware registers, and to table 8 for information on cpu/swim/debug module controller registers. gpio and peripheral registers 0x00 0000 reserved medium density (32 kbytes) reset and interrupt vectors 0x00 1000 0x00 10ff ram 0x00 07ff (2 kbytes) (1) (513 bytes) (1) 0x00 1100 data eeprom 0x00 4800 0x00 48ff 0x00 4900 0x00 7fff 0x00 8000 0x00 ffff 0x00 0800 0x00 0fff 0x00 47ff 0x00 7eff 0x00 8080 0x00 807f 0x00 7f00 reserved including stack (256 bytes) option bytes 0x00 4fff 0x00 5000 0x00 57ff 0x00 5800 reserved 0x00 5fff boot rom 0x00 6000 0x00 67ff (2 kbytes) 0x00 6800 reserved cpu/swim/debug/itc registers 0x00 5000 gpio ports 0x00 5050 flash 0x00 50c0 itc-exti 0x00 50d3 rst 0x00 50e0 clk 0x00 50f3 wwdg 0x00 5210 iwdg 0x00 5230 beep 0x00 5250 rtc 0x00 5280 spi1 0x00 52b0 i2c1 0x00 52e0 usart1 tim2 tim3 tim1 tim4 irtim adc1 0x00 5070 dma1 syscfg lcd ri 0x00 509e 0x00 50a0 0x00 50b0 0x00 5140 0x00 5200 0x00 52ff 0x00 5340 0x00 5380 0x00 5400 0x00 5430 0x00 5440 flash program memory wfe 0x00 50a6 0x00 50b2 pwr reserved reserved reserved memory and register map stm8l052c6 30/102 doc id 023331 rev 1 5.2 register map table 5. flash and ram boundary addresses memory area size start address end address ram 2 kbytes 0x00 0000 0x00 07ff flash program memory 32 kbytes 0x00 8000 0x00 ffff table 6. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x01 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pc_idr port c input pin value register 0xxx 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 stm8l052c6 memory and register map doc id 023331 rev 1 31/102 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 table 6. i/o port hardware register map (continued) address block register label register name reset status table 7. general hardware register map address block register label register name reset status 0x00 501e to 0x00 5049 reserved area (44 bytes) 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection key register 0x00 0x00 5053 flash _dukr data eeprom unprotection key register 0x00 0x00 5054 flash _iapsr flash in-application programming status register 0x00 0x00 5055 to 0x00 506f reserved area (27 bytes) memory and register map stm8l052c6 32/102 doc id 023331 rev 1 0x00 5070 dma1 dma1_gcsr dma1 global configuration & status register 0xfc 0x00 5071 dma1_gir1 dma1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 reserved area (3 bytes) 0x00 5075 dma1_c0cr dma1 channel 0 configuration register 0x00 0x00 5076 dma1_c0spr dma1 channel 0 status & priority register 0x00 0x00 5077 dma1_c0ndtr dma1 number of data to transfer register (channel 0) 0x00 0x00 5078 dma1_c0parh dma1 peripheral address high register (channel 0) 0x52 0x00 5079 dma1_c0parl dma1 peripheral address low register (channel 0) 0x00 0x00 507a reserved area (1 byte) 0x00 507b dma1_c0m0arh dma1 memory 0 address high register (channel 0) 0x00 0x00 507c dma1_c0m0arl dma1 memory 0 address low register (channel 0) 0x00 0x00 507d 0x00 507e reserved area (2 bytes) 0x00 507f dma1_c1cr dma1 channel 1 configuration register 0x00 0x00 5080 dma1_c1spr dma1 channel 1 status & priority register 0x00 0x00 5081 dma1_c1ndtr dma1 number of data to transfer register (channel 1) 0x00 0x00 5082 dma1_c1parh dma1 peripheral address high register (channel 1) 0x52 0x00 5083 dma1_c1parl dma1 peripheral address low register (channel 1) 0x00 table 7. general hardware register map (continued) address block register label register name reset status stm8l052c6 memory and register map doc id 023331 rev 1 33/102 0x00 5084 dma1 reserved area (1 byte) 0x00 5085 dma1_c1m0arh dma1 memory 0 address high register (channel 1) 0x00 0x00 5086 dma1_c1m0arl dma1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 reserved area (2 bytes) 0x00 5089 dma1_c2cr dma1 channel 2 configuration register 0x00 0x00 508a dma1_c2spr dma1 channel 2 status & priority register 0x00 0x00 508b dma1_c2ndtr dma1 number of data to transfer register (channel 2) 0x00 0x00 508c dma1_c2parh dma1 peripheral address high register (channel 2) 0x52 0x00 508d dma1_c2parl dma1 peripheral address low register (channel 2) 0x00 0x00 508e reserved area (1 byte) 0x00 508f dma1_c2m0arh dma1 memory 0 address high register (channel 2) 0x00 0x00 5090 dma1_c2m0arl dma1 memory 0 address low register (channel 2) 0x00 0x00 5091 0x00 5092 reserved area (2 bytes) 0x00 5093 dma1_c3cr dma1 channel 3 configuration register 0x00 0x00 5094 dma1_c3spr dma1 channel 3 status & priority register 0x00 0x00 5095 dma1_c3ndtr dma1 number of data to transfer register (channel 3) 0x00 0x00 5096 dma1_c3parh_ c3m1arh dma1 peripheral address high register (channel 3) 0x40 0x00 5097 dma1_c3parl_ c3m1arl dma1 peripheral address low register (channel 3) 0x00 0x00 5098 reserved area (1 byte) 0x00 5099 dma1_c3m0arh dma1 memory 0 address high register (channel 3) 0x00 0x00 509a dma1_c3m0arl dma1 memory 0 address low register (channel 3) 0x00 0x00 509b to 0x00 509d reserved area (3 bytes) 0x00 509e syscfg_rmpcr1 remapping register 1 0x00 0x00 509f syscfg_rmpcr2 remapping register 2 0x00 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052c6 34/102 doc id 023331 rev 1 0x00 50a0 itc - exti exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 exti_cr3 external interrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf1 external interrupt port select register 1 0x00 0x00 50a6 wfe wfe_cr1 wfe control register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 wfe_cr3 wfe control register 3 0x00 0x00 50ac to 0x00 50af reserved area (4 bytes) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 0x00 50b2 pwr pwr_csr1 power control and status register 1 0x00 0x00 50b3 pwr_csr2 power contro l and status register 2 0x00 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_divr clock master divider register 0x03 0x00 50c1 clk_crtcr clock rtc register 0x00 0x00 50c2 clk_ickr internal clock control register 0x11 0x00 50c3 clk_pckenr1 peripheral clock gating register 1 0x00 0x00 50c4 clk_pckenr2 peripheral clock gating register 2 0x80 0x00 50c5 clk_ccor configurable clock control register 0x00 0x00 50c6 clk_eckr external clock control register 0x00 0x00 50c7 clk_scsr system clock status register 0x01 0x00 50c8 clk_swr system clock switch register 0x01 0x00 50c9 clk_swcr clock switch control register 0bxxxx0000 0x00 50ca clk_cssr clock se curity system register 0x00 0x00 50cb clk_cbeepr clock beep register 0x00 0x00 50cc clk_hsicalr hsi calibration register 0xxx 0x00 50cd clk_hsitrimr hsi clock ca libration trimming register 0x00 0x00 50ce clk_hsiunlckr hsi unlock register 0x00 0x00 50cf clk_regcsr main regulator control status register 0bxx11100x 0x00 50d0 to 0x00 50d2 reserved area (3 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052c6 memory and register map doc id 023331 rev 1 35/102 0x00 50d3 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d4 wwdg_wr wwdr window register 0x7f 0x00 50d5 to 00 50df reserved area (11 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 beep beep_csr1 beep control/status register 1 0x00 0x00 50f1 0x00 50f2 reserved area (2 bytes) 0x00 50f3 beep_csr2 beep control/status register 2 0x1f 0x00 50f4 to 0x00 513f reserved area (76 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052c6 36/102 doc id 023331 rev 1 0x00 5140 rtc rtc_tr1 time register 1 0x00 0x00 5141 rtc_tr2 time register 2 0x00 0x00 5142 rtc_tr3 time register 3 0x00 0x00 5143 reserved area (1 byte) 0x00 5144 rtc_dr1 date register 1 0x01 0x00 5145 rtc_dr2 date register 2 0x21 0x00 5146 rtc_dr3 date register 3 0x00 0x00 5147 reserved area (1 byte) 0x00 5148 rtc_cr1 control register 1 0x00 0x00 5149 rtc_cr2 control register 2 0x00 0x00 514a rtc_cr3 control register 3 0x00 0x00 514b reserved area (1 byte) 0x00 514c rtc_isr1 initialization and status register 1 0x00 0x00 514d rtc_isr2 initializatio n and status register 2 0x00 0x00 514e 0x00 514f reserved area (2 bytes) 0x00 5150 rtc_sprerh (1) synchronous prescaler register high 0x00 (1) 0x00 5151 rtc_sprerl (1) synchronous prescaler register low 0xff (1) 0x00 5152 rtc_aprer (1) asynchronous prescaler register 0x7f (1) 0x00 5153 reserved area (1 byte) 0x00 5154 rtc_wutrh (1) wakeup timer register high 0xff (1) 0x00 5155 rtc_wutrl (1) wakeup timer register low 0xff (1) 0x00 5156 to 0x00 5158 reserved area (3 bytes) 0x00 5159 rtc_wpr write protection register 0x00 0x00 515a 0x00 515b reserved area (2 bytes) 0x00 515c rtc_alrmar1 alarm a register 1 0x00 0x00 515d rtc_alrmar2 alarm a register 2 0x00 0x00 515e rtc_alrmar3 alarm a register 3 0x00 0x00 515f rtc_alrmar4 alarm a register 4 0x00 0x00 5160 to 0x00 51ff reserved area (160 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052c6 memory and register map doc id 023331 rev 1 37/102 0x00 5200 spi1 spi1_cr1 spi1 control register 1 0x00 0x00 5201 spi1_cr2 spi1 control register 2 0x00 0x00 5202 spi1_icr spi1 interrupt control register 0x00 0x00 5203 spi1_sr spi1 st atus register 0x02 0x00 5204 spi1_dr spi1 data register 0x00 0x00 5205 spi1_crcpr spi1 crc polynomial register 0x07 0x00 5206 spi1_rxcrcr spi1 rx crc register 0x00 0x00 5207 spi1_txcrcr spi1 tx crc register 0x00 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i2c1 i2c1_cr1 i2c1 control register 1 0x00 0x00 5211 i2c1_cr2 i2c1 control register 2 0x00 0x00 5212 i2c1_freqr i2c1 frequency register 0x00 0x00 5213 i2c1_oarl i2c1 own address register low 0x00 0x00 5214 i2c1_oarh i2c1 own address register high 0x00 0x00 5215 reserved (1 byte) 0x00 5216 i2c1_dr i2c1 data register 0x00 0x00 5217 i2c1_sr1 i2c1 status register 1 0x00 0x00 5218 i2c1_sr2 i2c1 status register 2 0x00 0x00 5219 i2c1_sr3 i2c1 status register 3 0x0x 0x00 521a i2c1_itr i2c1 interrupt control register 0x00 0x00 521b i2c1_ccrl i2c1 clock control register low 0x00 0x00 521c i2c1_ccrh i2c1 clock control register high 0x00 0x00 521d i2c1_triser i2c1 trise register 0x02 0x00 521e i2c1_pecr i2c1 packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052c6 38/102 doc id 023331 rev 1 0x00 5230 usart1 usart1_sr usart1 status register 0xc0 0x00 5231 usart1_dr usart1 data register undefined 0x00 5232 usart1_brr1 usart1 baud rate register 1 0x00 0x00 5233 usart1_brr2 usart1 baud rate register 2 0x00 0x00 5234 usart1_cr1 usart1 control register 1 0x00 0x00 5235 usart1_cr2 usart1 control register 2 0x00 0x00 5236 usart1_cr3 usart1 control register 3 0x00 0x00 5237 usart1_cr4 usart1 control register 4 0x00 0x00 5238 usart1_cr5 usart1 control register 5 0x00 0x00 5239 usart1_gtr usart1 guard time register 0x00 0x00 523a usart1_pscr usart1 prescaler register 0x00 0x00 523b to 0x00 524f reserved area (21 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052c6 memory and register map doc id 023331 rev 1 39/102 0x00 5250 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5251 tim2_cr2 tim2 control register 2 0x00 0x00 5252 tim2_smcr tim2 slave mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_der tim2 dma1 request enable register 0x00 0x00 5255 tim2_ier tim2 interrupt enable register 0x00 0x00 5256 tim2_sr1 tim2 st atus register 1 0x00 0x00 5257 tim2_sr2 tim2 st atus register 2 0x00 0x00 5258 tim2_egr tim2 event generation register 0x00 0x00 5259 tim2_ccmr1 tim2 captur e/compare mode register 1 0x00 0x00 525a tim2_ccmr2 tim2 capture/compare mode register 2 0x00 0x00 525b tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 525c tim2_cntrh tim2 counter high 0x00 0x00 525d tim2_cntrl tim2 counter low 0x00 0x00 525e tim2_pscr tim2 prescaler register 0x00 0x00 525f tim2_arrh tim2 auto-reload register high 0xff 0x00 5260 tim2_arrl tim2 auto-reload register low 0xff 0x00 5261 tim2_ccr1h tim2 capture/ compare register 1 high 0x00 0x00 5262 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5263 tim2_ccr2h tim2 capture/ compare register 2 high 0x00 0x00 5264 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5265 tim2_bkr tim2 break register 0x00 0x00 5266 tim2_oisr tim2 outpu t idle state register 0x00 0x00 5267 to 0x00 527f reserved area (25 bytes) table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052c6 40/102 doc id 023331 rev 1 0x00 5280 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5281 tim3_cr2 tim3 control register 2 0x00 0x00 5282 tim3_smcr tim3 slave mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_der tim3 dma1 request enable register 0x00 0x00 5285 tim3_ier tim3 interrupt enable register 0x00 0x00 5286 tim3_sr1 tim3 st atus register 1 0x00 0x00 5287 tim3_sr2 tim3 st atus register 2 0x00 0x00 5288 tim3_egr tim3 event generation register 0x00 0x00 5289 tim3_ccmr1 tim3 captur e/compare mode register 1 0x00 0x00 528a tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 528b tim3_ccer1 tim3 capture/compare enable register 1 0x00 0x00 528c tim3_cntrh tim3 counter high 0x00 0x00 528d tim3_cntrl tim3 counter low 0x00 0x00 528e tim3_pscr tim3 prescaler register 0x00 0x00 528f tim3_arrh tim3 auto-reload register high 0xff 0x00 5290 tim3_arrl tim3 auto-reload register low 0xff 0x00 5291 tim3_ccr1h tim3 capture/ compare register 1 high 0x00 0x00 5292 tim3_ccr1l tim3 captur e/compare register 1 low 0x00 0x00 5293 tim3_ccr2h tim3 capture/ compare register 2 high 0x00 0x00 5294 tim3_ccr2l tim3 captur e/compare register 2 low 0x00 0x00 5295 tim3_bkr tim3 break register 0x00 0x00 5296 tim3_oisr tim3 outpu t idle state register 0x00 0x00 5297 to 0x00 52af reserved area (25 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052c6 memory and register map doc id 023331 rev 1 41/102 0x00 52b0 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 52b1 tim1_cr2 tim1 control register 2 0x00 0x00 52b2 tim1_smcr tim1 slave mode control register 0x00 0x00 52b3 tim1_etr tim1 external trigger register 0x00 0x00 52b4 tim1_der tim1 dma1 request enable register 0x00 0x00 52b5 tim1_ier tim1 interrupt enable register 0x00 0x00 52b6 tim1_sr1 tim1 status register 1 0x00 0x00 52b7 tim1_sr2 tim1 status register 2 0x00 0x00 52b8 tim1_egr tim1 event generation register 0x00 0x00 52b9 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 52ba tim1_ccmr2 tim1 captur e/compare mode register 2 0x00 0x00 52bb tim1_ccmr3 tim1 captur e/compare mode register 3 0x00 0x00 52bc tim1_ccmr4 tim1 captur e/compare mode register 4 0x00 0x00 52bd tim1_ccer1 tim1 capture/compare enable register 1 0x00 0x00 52be tim1_ccer2 tim1 capture/compare enable register 2 0x00 0x00 52bf tim1_cntrh tim1 counter high 0x00 0x00 52c0 tim1_cntrl tim1 counter low 0x00 0x00 52c1 tim1_pscrh tim1 prescaler register high 0x00 0x00 52c2 tim1_pscrl tim1 prescaler register low 0x00 0x00 52c3 tim1_arrh tim1 auto-reload register high 0xff 0x00 52c4 tim1_arrl tim1 auto-reload register low 0xff 0x00 52c5 tim1_rcr tim1 repetition counter register 0x00 0x00 52c6 tim1_ccr1h tim1 capture/ compare register 1 high 0x00 0x00 52c7 tim1_ccr1l tim1 capture/compare register 1 low 0x00 0x00 52c8 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 52c9 tim1_ccr2l tim1 capture/compare register 2 low 0x00 0x00 52ca tim1_ccr3h tim1 captur e/compare register 3 high 0x00 0x00 52cb tim1_ccr3l tim1 captur e/compare register 3 low 0x00 0x00 52cc tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 52cd tim1_ccr4l tim1 captur e/compare register 4 low 0x00 0x00 52ce tim1_bkr tim1 break register 0x00 0x00 52cf tim1_dtr tim1 dead-time register 0x00 0x00 52d0 tim1_oisr tim1 outpu t idle state register 0x00 0x00 52d1 tim1_dcr1 dma1 control register 1 0x00 table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052c6 42/102 doc id 023331 rev 1 0x00 52d2 tim1 tim1_dcr2 tim1 dma1 control register 2 0x00 0x00 52d3 tim1_dma1r tim1 dma1 address for burst mode 0x00 0x00 52d4 to 0x00 52df reserved area (12 bytes) 0x00 52e0 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slave mode control register 0x00 0x00 52e3 tim4_der tim4 dma1 request enable register 0x00 0x00 52e4 tim4_ier tim4 interrupt enable register 0x00 0x00 52e5 tim4_sr1 tim4 status register 1 0x00 0x00 52e6 tim4_egr tim4 event generation register 0x00 0x00 52e7 tim4_cntr tim4 counter 0x00 0x00 52e8 tim4_pscr tim4 prescaler register 0x00 0x00 52e9 tim4_arr tim4 auto-reload register 0x00 0x00 52ea to 0x00 52fe reserved area (21 bytes) 0x00 52ff irtim ir_cr infrared control register 0x00 0x00 5300 to 0x00 533f reserved area (64 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052c6 memory and register map doc id 023331 rev 1 43/102 0x00 5340 adc1 adc1_cr1 adc1 configuration register 1 0x00 0x00 5341 adc1_cr2 adc1 configuration register 2 0x00 0x00 5342 adc1_cr3 adc1 configuration register 3 0x1f 0x00 5343 adc1_sr adc1 status register 0x00 0x00 5344 adc1_drh adc1 data register high 0x00 0x00 5345 adc1_drl adc1 data register low 0x00 0x00 5346 adc1_htrh adc1 high threshold register high 0x0f 0x00 5347 adc1_htrl adc1 high threshold register low 0xff 0x00 5348 adc1_ltrh adc1 low threshold register high 0x00 0x00 5349 adc1_ltrl adc1 low threshold register low 0x00 0x00 534a adc1_sqr1 adc1 channel sequence 1 register 0x00 0x00 534b adc1_sqr2 adc1 channel sequence 2 register 0x00 0x00 534c adc1_sqr3 adc1 channel sequence 3 register 0x00 0x00 534d adc1_sqr4 adc1 channel sequence 4 register 0x00 0x00 534e adc1_trigr1 adc1 trigger disable 1 0x00 0x00 534f adc1_trigr2 adc1 trigger disable 2 0x00 0x00 5350 adc1_trigr3 adc1 trigger disable 3 0x00 0x00 5351 adc1_trigr4 adc1 trigger disable 4 0x00 0x00 5352 to 0x00 53ff reserved area (174 bytes) 0x00 5400 lcd lcd_cr1 lcd control register 1 0x00 0x00 5401 lcd_cr2 lcd control register 2 0x00 0x00 5402 lcd_cr3 lcd control register 3 0x00 0x00 5403 lcd_frq lcd frequency selection register 0x00 0x00 5404 lcd_pm0 lcd port mask register 0 0x00 0x00 5405 lcd_pm1 lcd port mask register 1 0x00 0x00 5406 lcd_pm2 lcd port mask register 2 0x00 0x00 5407 reserved area table 7. general hardware register map (continued) address block register label register name reset status memory and register map stm8l052c6 44/102 doc id 023331 rev 1 0x00 5408 to 0x00 540b lcd reserved area (4 bytes) 0x00 540c lcd_ram0 lcd display memory 0 0x00 0x00 540d lcd_ram1 lcd display memory 1 0x00 0x00 540e lcd_ram2 lcd display memory 2 0x00 0x00 540f lcd_ram3 lcd display memory 3 0x00 0x00 5410 lcd_ram4 lcd display memory 4 0x00 0x00 5411 lcd_ram5 lcd display memory 5 0x00 0x00 5412 lcd_ram6 lcd display memory 6 0x00 0x00 5413 lcd_ram7 lcd display memory 7 0x00 0x00 5414 lcd_ram8 lcd display memory 8 0x00 0x00 5415 lcd_ram9 lcd display memory 9 0x00 0x00 5416 lcd_ram10 lcd display memory 10 0x00 0x00 5417 lcd_ram11 lcd display memory 11 0x00 0x00 5418 lcd_ram12 lcd display memory 12 0x00 0x00 5419 lcd_ram13 lcd display memory 13 0x00 0x00 541a to 0x00 542f reserved area (22 bytes) table 7. general hardware register map (continued) address block register label register name reset status stm8l052c6 memory and register map doc id 023331 rev 1 45/102 0x00 5430 ri reserved area (1 byte) 0x00 0x00 5431 ri_icr1 timer input capt ure routing register 1 0x00 0x00 5432 ri_icr2 timer input capt ure routing register 2 0x00 0x00 5433 ri_ioir1 i/o input register 1 undefined 0x00 5434 ri_ioir2 i/o input register 2 undefined 0x00 5435 ri_ioir3 i/o input register 3 undefined 0x00 5436 ri_iocmr1 i/o control mode register 1 0x00 0x00 5437 ri_iocmr2 i/o control mode register 2 0x00 0x00 5438 ri_iocmr3 i/o control mode register 3 0x00 0x00 5439 ri_iosr1 i/o switch register 1 0x00 0x00 543a ri_iosr2 i/o switch register 2 0x00 0x00 543b ri_iosr3 i/o switch register 3 0x00 0x00 543c ri_iogcr i/o group control register 0x3f 0x00 543d ri_ascr1 analog switch register 1 0x00 0x00 543e ri_ascr2 analog switch register 2 0x00 0x00 543f ri_rcr resistor co ntrol register 1 0x00 0x00 5440 to 0x00 5444 reserved area (5 bytes) 1. these registers are not impacted by a sy stem reset. they are reset at power-on. table 7. general hardware register map (continued) address block register label register name reset status table 8. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 memory and register map stm8l052c6 46/102 doc id 023331 rev 1 0x00 7f0b to 0x00 7f5f cpu reserved area (85 bytes) 0x00 7f60 cfg_gcr global configuration register 0x00 0x00 7f70 itc-spr itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only table 8. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status stm8l052c6 interrupt vector mapping doc id 023331 rev 1 47/102 6 interrupt vector mapping table 9. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active- halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address reset reset yes yes yes yes 0x00 8000 trap software interrupt - - - - 0x00 8004 0 reserved 0x00 8008 1 flash flash end of programing/ write attempted to protected page interrupt - - yes yes 0x00 800c 2 dma1 0/1 dma1 channels 0/1 half transaction/transaction complete interrupt - - yes yes 0x00 8010 3 dma1 2/3 dma1 channels 2/3 half transaction/transaction complete interrupt - - yes yes 0x00 8014 4rtc rtc alarm a/ wakeup yes yes yes yes 0x00 8018 5 exti e/f/ pvd (2) external interrupt port e/f pvd interrupt yes yes yes yes 0x00 801c 6 extib/g external interrupt port b/g yes yes yes yes 0x00 8020 7 extid/h external interrupt port d/h yes yes yes yes 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes 0x00 8044 16 lcd lcd interrupt - - yes yes 0x00 8048 17 clk/tim1 clk system clock switch/ css interrupt/ tim 1 break - - yes yes 0x00 804c 18 adc1 acd1 end of conversion/ analog watchdog/ overrun interrupt yes yes yes yes 0x00 8050 interrupt vector mapping stm8l052c6 48/102 doc id 023331 rev 1 19 tim2 tim2 update/overflow/ trigger/break interrupt - - yes yes 0x00 8054 20 tim2 tim2capture/ compare interrupt - - yes yes 0x00 8058 21 tim3 tim3 update/overflow/ trigger/break interrupt - - yes yes 0x00 805c 22 tim3 tim3 capture/compare interrupt - - yes yes 0x00 8060 23 tim1 update /overflow/trigger/ com - - - yes 0x00 8064 24 tim1 capture/compare - - - yes 0x00 8068 25 tim4 tim4 update/overflow/ trigger interrupt - - yes yes 0x00 806c 26 spi1 spi1 tx buffer empty/ rx buffer not empty/ error/wakeup interrupt yes yes yes yes 0x00 8070 27 usart1 usart1transmit data register empty/ transmission complete interrupt - - yes yes 0x00 8074 28 usart1 usart1 received data ready/overrun error/ idle line detected/parity error/global error interrupt - - yes yes 0x00 8078 29 i 2 c1 i 2 c1 interrupt (3) yes yes yes yes 0x00 807c 1. the low power wait mode is entered when executing a wf e instruction in low power run mode. in wfe mode, the interrupt is served if it has been previ ously enabled. after processi ng the interrupt, the processor goes back to wfe mode. when the interrupt is configured as a wakeup event, the cpu wakes up and resumes processing. 2. the interrupt from pvd is logically or- ed with port e and f interrupts. register exti_conf allows to select between port e and port f interrupt (see external interrupt port sele ct register (exti_conf) in the rm0031). 3. the device is woken up from halt or active-halt mode only when the address received matches the interface address. table 9. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active- halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address stm8l052c6 option bytes doc id 023331 rev 1 49/102 7 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated memory block. all option bytes can be modified in icp mode (with swim) by accessing the eeprom address. see ta b l e 1 0 for details on option byte addresses. the option bytes can also be modified ?on the fly? by the application in iap mode, except for the rop and ubc values which can only be taken into account when they are modified in icp mode (with the swim). refer to the stm8lxx flash programming manual (pm0054) and stm8 swim and debug manual (um0470) for information on swim programming procedures. table 10. option byte addresses addr. option name option byte no. option bits factory default setting 76543210 0x00 4800 read-out protection (rop) opt0 rop[7:0] 0xaa 0x00 4802 ubc (user boot code size) opt1 ubc[7:0] 0x00 0x00 4807 reserved 0x00 0x00 4808 independent watchdog option opt3 [3:0] reserved wwdg _halt wwdg _hw iwdg _halt iwdg _hw 0x00 0x00 4809 number of stabilization clock cycles for hse and lse oscillators opt4 reserved lsecnt[1:0] hsecnt[1:0] 0x00 0x00 480a brownout reset (bor) opt5 [3:0] reserved bor_th bor_ on 0x01 0x00 480b bootloader option bytes (optbl) optbl [15:0] optbl[15:0] 0x00 0x00 480c 0x00 option bytes stm8l052c6 50/102 doc id 023331 rev 1 table 11. option byte description option byte no. option description opt0 rop[7:0] memory readout protection (rop) 0xaa: disable readout protection (write access via swim protocol) refer to readout protection section in t he stm8l05x/15x and stm8l16x reference manual (rm0031). opt1 ubc[7:0] size of the user boot code area 0x00: no ubc 0x01: the ubc contains only the interrupt vectors. 0x02: page 0 and 1 reserved for the ubc and read/writ e protected. page 0 contai ns only the interrupt vectors. 0x03 - page 0 to 2 reserved for ubc, memory write-protected 0xff - page 0 to 254 reserved for ubc, memory write-protected refer to user boot code section in the stm8l 05x/15x and stm8l16x re ference manual (rm0031). opt2 reserved opt3 iwdg_hw: independent watchdog 0: independent watchdog activated by software 1: independent watchdog activated by hardware iwdg_halt: independent window watchdog off on halt/active-halt 0: independent watchdog continues running in halt/active-halt mode 1: independent watchdog stopped in halt/active-halt mode wwdg_hw: window watchdog 0: window watchdog activated by software 1: window watchdog activated by hardware wwdg_halt: window window watchdog reset on halt/active-halt 0: window watchdog stopped in halt mode 1: window watchdog generates a reset when mcu enters halt mode opt4 hsecnt : number of hse oscillato r stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles lsecnt : number of lse oscillat or stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles refer to table 29: lse oscillator characteristics on page 69 . stm8l052c6 option bytes doc id 023331 rev 1 51/102 opt5 bor_on : 0: brownout reset off 1: brownout reset on bor_th[3:1] : brownout reset thresholds. refer to ta b l e 2 0 for details on the thresholds according to the value of bor_th bits. optbl optbl[15:0] : this option is checked by the boot rom code after reset. depending on content of addresses 00 480b, 00 480c and 0x8000 (reset vector) the cpu jumps to the bootloader or to the reset vector. refer to the um0560 bootloader user manual for more details. table 11. option byte description (continued) option byte no. option description electrical parameters stm8l052c6 52/102 doc id 023331 rev 1 8 electrical parameters 8.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 8.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics is indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 8.1.2 typical values unless otherwise specified, typical data is based on t a = 25 c, v dd = 3 v. it is given only as design guidelines and is not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 8.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 8.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 5 . figure 5. pin loading conditions 50 pf stm8l pin stm8l052c6 electrical parameters doc id 023331 rev 1 53/102 8.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 6 . figure 6. pin input voltage 8.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in stm8l pin table 12. voltage characteristics symbol ratings min max unit v dd - v ss external supply voltage (including v dda and v dd2 ) (1) 1. all power (v dd1 , v dd2 , v dda ) and ground (v ss1 , v ss2 , v ssa ) pins must always be connected to the external power supply. - 0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 13. for maximum allowed injected current values. input voltage on true open-drain pins (pc0 and pc1) v ss - 0.3 v dd + 4.0 v input voltage on five-volt tolerant (ft) pins (pa7 and pe0) v ss - 0.3 v dd + 4.0 input voltage on 3.6 v tolerant (tt) pins v ss - 0.3 4.0 input voltage on any other pin v ss - 0.3 4.0 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 95 electrical parameters stm8l052c6 54/102 doc id 023331 rev 1 table 13. current characteristics symbol ratings max. unit i vdd total current into v dd power line (source) 80 ma i vss total current out of v ss ground line (sink) 80 i io output current sunk by ir_tim pin (with high sink led driver capability) 80 output current sunk by any other i/o and control pin 25 output current sourced by any i/os and control pin - 25 i inj(pin) injected current on true open-drain pins (pc0 and pc1) (1) - 5 / +0 injected current on five-volt tolerant (ft) pins (pa7 and pe0) (1) 1. positive injection is not possible on thes e i/os. a negative injection is induced by v in electrical parameters stm8l052c6 56/102 doc id 023331 rev 1 8.3.2 embedded reset and power control block characteristics table 16. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd v dd rise time rate bor detector enabled 0 (1) (1) s/v v dd fall time rate bor detector enabled 20 (1) (1) t temp reset release delay v dd rising 3ms v pdr power-down reset threshold falling edge 1.30 (2) 1.50 1.65 v v bor0 brown-out reset threshold 0 (bor_th[2:0]=000) falling edge 1.67 1.70 1.74 v rising edge 1.69 1.75 1.80 v bor1 brown-out reset threshold 1 (bor_th[2:0]=001) falling edge 1.87 1.93 1.97 rising edge 1.96 2.04 2.07 v bor2 brown-out reset threshold 2 (bor_th[2:0]=010) falling edge 2.22 2.3 2.35 rising edge 2.31 2.41 2.44 v bor3 brown-out reset threshold 3 (bor_th[2:0]=011) falling edge 2.45 2.55 2.60 rising edge 2.54 2.66 2.7 v bor4 brown-out reset threshold 4 (bor_th[2:0]=100) falling edge 2.68 2.80 2.85 rising edge 2.78 2.90 2.95 v pvd0 pvd threshold 0 falling edge 1.80 1.84 1.88 v rising edge 1.88 1.94 1.99 v pvd1 pvd threshold 1 falling edge 1.98 2.04 2.09 rising edge 2.08 2.14 2.18 v pvd2 pvd threshold 2 falling edge 2.2 2.24 2.28 rising edge 2.28 2.34 2.38 v pvd3 pvd threshold 3 falling edge 2.39 2.44 2.48 rising edge 2.47 2.54 2.58 v pvd4 pvd threshold 4 falling edge 2.57 2.64 2.69 rising edge 2.68 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.77 2.83 2.88 rising edge 2.87 2.94 2.99 v pvd6 pvd threshold 6 falling edge 2.97 3.05 3.09 rising edge 3.08 3.15 3.20 1. data guaranteed by design, not tested in production. 2. data based on characterization results, not tested in production. stm8l052c6 electrical parameters doc id 023331 rev 1 57/102 figure 7. por/bor thresholds 8.3.3 supply current characteristics total current consumption the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if explicitly mentioned. in the following table, data is based on characterization results, unless otherwise specified. subject to general operating conditions for v dd and t a . 1.8 v vdd internal nrst v bor0 bor threshold bor threshold_0 pdr threshold with bor without bor time with bor safe reset reset at power up bor activated by user for power down detection vdd vdd operating power supply 3.6 v without bor = batte ry li fe exte nsi on v pdr safe reset release bor always active electrical parameters stm8l052c6 58/102 doc id 023331 rev 1 table 17. total current consumption in run mode symbol para meter conditions (1) 1. all peripherals off, v dd from 1.8 v to 3.6 v, hsi internal rc osc. , f cpu =f sysclk typ max unit 55 c 85 c i dd(run) supply current in run mode (2) 2. cpu executing typi cal data processing all peripherals off, code executed from ram, v dd from 1.8 v to 3.6 v hsi rc osc. (16 mhz) (3) 3. the run from ram consumption can be approximated with the linear formula: i dd (run_from_ram) = freq * 90 a/mhz + 380 a f cpu = 125 khz 0.39 0.47 0.49 ma f cpu = 1 mhz 0.48 0.56 0.58 f cpu = 4 mhz 0.75 0.84 0.86 f cpu = 8 mhz 1.10 1.20 1.25 f cpu = 16 mhz 1.85 1.93 2.12 (5) hse external clock (f cpu =f hse ) (4) f cpu = 125 khz 0.05 0.06 0.09 f cpu = 1 mhz 0.18 0.19 0.20 f cpu = 4 mhz 0.55 0.62 0.64 f cpu = 8 mhz 0.99 1.20 1.21 f cpu = 16 mhz 1.90 2.22 2.23 (5) lsi rc osc. (typ. 38 khz) f cpu = f lsi 0.040 0.045 0.046 lse external clock (32.768 khz) f cpu = f lse 0.035 0.040 0.048 (5) i dd(run) supply current in run mode all peripherals off, code executed from flash, v dd from 1.8 v to 3.6 v hsi rc osc. (6) f cpu = 125 khz 0.43 0.55 0.56 ma f cpu = 1 mhz 0.60 0.77 0.80 f cpu = 4 mhz 1.11 1.34 1.37 f cpu = 8 mhz 1.90 2.20 2.23 f cpu = 16 mhz 3.8 4.60 4.75 hse external clock (f cpu =f hse ) (4) f cpu = 125 khz 0.30 0.36 0.39 f cpu = 1 mhz 0.40 0.50 0.52 f cpu = 4 mhz 1.15 1.31 1.40 f cpu = 8 mhz 2.17 2.33 2.44 f cpu = 16 mhz 4.0 4.46 4.52 lsi rc osc. f cpu = f lsi 0.110 0.123 0.130 lse ext. clock (32.768 khz) (7) f cpu = f lse 0.100 0.101 0.104 stm8l052c6 electrical parameters doc id 023331 rev 1 59/102 figure 8. typ. i dd(run) vs. v dd ,f cpu = 16mhz 1. typical current consumption meas ured with code executed from ram 4. oscillator bypassed (hsebyp = 1 in clk_eckcr). when configured for external crystal, the hse consumption (i dd hse ) must be added. refer to table 28 . 5. tested in production. 6. the run from flash consumption can be approximated with the linear formula: i dd (run_from_flash) = freq * 195 a/mhz + 440 a 7. oscillator bypassed (lsebyp = 1 in clk_eckcr). when configured for extenal crystal, the lse consumption (i dd lse ) must be added. refer to table 29 . 1.50 1.75 2.00 2.25 2.50 2.75 3.00 1.8 2.1 2.6 3.1 3.6 v dd [v] idd(run)hsi [ma] -40c 25c 85c ai18213v2 electrical parameters stm8l052c6 60/102 doc id 023331 rev 1 in the following table, data is based on characterization results, unless otherwise specified. table 18. total current consumption in wait mode symbol parameter conditions (1) 1. all peripherals off, v dd from 1.8 v to 3.6 v, hsi internal rc osc. , f cpu = f sysclk typ max unit 55c 85 c (2) 2. for temperature range 6. i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from ram with flash in i ddq mode (3) , v dd from 1.8 v to 3.6 v 3. flash is configured in i ddq mode in wait mode by setting the epm or waitm bit in the flash_cr1 register. hsi f cpu = 125 khz 0.33 0.39 0.41 ma f cpu = 1 mhz 0.35 0.41 0.44 f cpu = 4 mhz 0.42 0.51 0.52 f cpu = 8 mhz 0.52 0.57 0.58 f cpu = 16 mhz 0.68 0.76 0.79 hse external clock (f cpu =f hse ) (4) f cpu = 125 khz 0.032 0.056 0.068 f cpu = 1 mhz 0.078 0.121 0.144 f cpu = 4 mhz 0.218 0.26 0.30 f cpu = 8 mhz 0.40 0.52 0.57 f cpu = 16 mhz 0.760 1.01 1.05 lsi f cpu = f lsi 0.035 0.044 0.046 lse (5) external clock (32.768 khz) f cpu = f lse 0.032 0.036 0.038 i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from flash, v dd from 1.8 v to 3.6 v hsi f cpu = 125 khz 0.38 0.48 0.49 ma f cpu = 1 mhz 0.41 0.49 0.51 f cpu = 4 mhz 0.50 0.57 0.58 f cpu = 8 mhz 0.60 0.66 0.68 f cpu = 16 mhz 0.79 0.84 0.86 hse (4) external clock (f cpu =hse) f cpu = 125 khz 0.06 0.08 0.09 f cpu = 1 mhz 0.10 0.17 0.18 f cpu = 4 mhz 0.24 0.36 0.39 f cpu = 8 mhz 0.50 0.58 0.61 f cpu = 16 mhz 1.00 1.08 1.14 lsi f cpu = f lsi 0.055 0.058 0.065 lse (5) external clock (32.768 khz) f cpu = f lse 0.051 0.056 0.060 stm8l052c6 electrical parameters doc id 023331 rev 1 61/102 figure 9. typ. i dd(wait) vs. v dd ,f cpu =16mhz 1) 1. typical current consumption measured with code executed from flash memory. 4. oscillator bypassed (hsebyp = 1 in clk_eckcr). when configured for external crystal, the hse consumption (i dd hse ) must be added. refer to table 28 . 5. oscillator bypassed (lsebyp = 1 in clk_eckcr). when configured for extenal crystal, the lse consumption (i dd hse ) must be added. refer to table 29 . 500 550 600 650 700 750 800 850 900 950 1000 1.8 2.1 2.6 3.1 3.6 v dd [v] idd(wait)hsi [a] -40c 25c 85c ai18214v2 electrical parameters stm8l052c6 62/102 doc id 023331 rev 1 in the following table, data is based on characterization results, unless otherwise specified. figure 10. typ. i dd(lpr) vs. v dd (lsi clock source) table 19. total current consumption and timing in low power run mode at v dd = 1.8 v to 3.6 v symbol parameter conditions (1) typ max unit i dd(lpr) supply current in low power run mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 5.1 5.4 a t a = 55 c 5.7 6 t a = 85 c 6.8 7.5 with tim2 active (2) t a = -40 c to 25 c 5.4 5.7 t a = 55 c 6.0 6.3 t a = 85 c 7.2 7.8 lse (3) external clock (32.768 khz) all peripherals off t a = -40 c to 25 c 5.25 5.6 t a = 55 c 5.67 6.1 t a = 85 c 5.85 6.3 with tim2 active (2) t a = -40 c to 25 c 5.59 6 t a = 55 c 6.10 6.4 t a = 85 c 6.30 7 1. no floating i/os 2. timer 2 clock enabl ed and counter running 3. oscillator bypassed (lsebyp = 1 in clk_eckcr). when configured for extenal crystal, the lse consumption (i dd lse ) must be added. refer to table 29 0 2 4 6 8 10 12 14 16 18 1 . 8 2.1 2.6 3.1 3.6 v dd [v] ai18216v2 i dd(lpr)lsi [a] C40 c 25 c 85 c stm8l052c6 electrical parameters doc id 023331 rev 1 63/102 in the following table, data is based on characterization results, unless otherwise specified. figure 11. typ. i dd(lpw) vs. v dd (lsi clock source) table 20. total current consumption in low power wait mode at v dd = 1.8v to 3.6v symbol parameter conditions (1) typ max unit i dd(lpw) supply current in low power wait mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 33.3 a t a = 55 c 3.3 3.6 t a = 85 c 4.4 5 with tim2 active (2) t a = -40 c to 25 c 3.4 3.7 t a = 55 c 3.7 4 t a = 85 c 4.8 5.4 lse external clock (3) (32.768 khz) all peripherals off t a = -40 c to 25 c 2.35 2.7 t a = 55 c 2.42 2.82 t a = 85 c 3.10 3.71 with tim2 active (2) t a = -40 c to 25 c 2.46 2.75 t a = 55 c 2.50 2.81 t a = 85 c 3.16 3.82 1. no floating i/os. 2. timer 2 clock enabled and counter is running. 3. oscillator bypassed (lsebyp = 1 in clk_eckcr). when configured for extenal crystal, the lse consumption (i dd lse ) must be added. refer to table 29 . 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 1.8 2.1 2.6 3.1 3.6 v dd [v] i dd(lpw )lsi [a] -40c 25c 85c ai18217v2 electrical parameters stm8l052c6 64/102 doc id 023331 rev 1 in the following table, data is based on characterization results, unless otherwise specified. table 21. total current consumption and timing in active-halt mode at v dd = 1.8 v to 3.6 v symbol parameter conditions (1) typ max unit i dd(ah) supply current in active-halt mode lsi rc (at 38 khz) lcd off (2) t a = -40 c to 25 c 0.9 2.1 a t a = 55 c 1.2 3 t a = 85 c 1.5 3.4 lcd on (static duty/ external v lcd ) (3) t a = -40 c to 25 c 1.4 3.1 t a = 55 c 1.5 3.3 t a = 85 c 1.9 4.3 lcd on (1/4 duty/ external v lcd ) (4) t a = -40 c to 25 c 1.9 4.3 t a = 55 c 1.95 4.4 t a = 85 c 2.4 5.4 lcd on (1/4 duty/ internal v lcd ) (5) t a = -40 c to 25 c 3.9 8.75 t a = 55 c 4.15 9.3 t a = 85 c 4.5 10.2 i dd(ah) supply current in active-halt mode lse external clock (32.768 khz) (6) lcd off (7) t a = -40 c to 25 c 0.5 1.2 a t a = 55 c 0.62 1.4 t a = 85 c 0.88 2.1 lcd on (static duty/ external v lcd ) (3) t a = -40 c to 25 c 0.85 1.9 t a = 55 c 0.95 2.2 t a = 85 c 1.3 3.2 lcd on (1/4 duty/ external v lcd ) (4) t a = -40 c to 25 c 1.5 2.5 t a = 55 c 1.6 3.8 t a = 85 c 1.8 4.2 lcd on (1/4 duty/ internal v lcd ) (5) t a = -40 c to 25 c 3.4 7.6 t a = 55 c 3.7 8.3 t a = 85 c 3.9 9.2 i dd(wufah) supply current during wakeup time from active-halt mode (using hsi) 2.4 ma t wu_hsi(ah) (8)(9) wakeup time from active-halt mode to run mode (using hsi) 4.7 7 s t wu_lsi(ah) (8) (9) wakeup time from active-halt mode to run mode (using lsi) 150 s 1. no floating i/o, unles s otherwise specified. 2. rtc enabled. clock source = lsi 3. rtc enabled, lcd enabled with external v lcd = 3 v, static duty, division ratio = 256, all pixels active, no lcd connected. stm8l052c6 electrical parameters doc id 023331 rev 1 65/102 in the following table, data is based on characterization results, unless otherwise specified. 4. rtc enabled, lcd enabled with external v lcd , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no lcd connected. 5. lcd enabled with internal lcd booster v lcd = 3 v , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no lcd connected. 6. oscillator bypassed (lsebyp = 1 in clk_eckcr). when configured for extenal crystal, the lse consumption (i dd lse ) must be added. refer to table 29 . 7. rtc enabled. clock source = lse. 8. wakeup time until start of interrupt vector fetch. the first word of interrupt routi ne is fetched 4 cpu cycles after t wu . 9. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register. table 22. typical current consumption in active-halt mode, rtc clocked by lse external crystal symbol parameter condition (1) typ unit i dd(ah) (2) supply current in active-halt mode v dd = 1.8 v lse 1.15 a lse/32 (3) 1.05 v dd = 3 v lse 1.30 lse/32 (3) 1.20 v dd = 3.6 v lse 1.45 lse/32 (3) 1.35 1. no floating i/o, unles s otherwise specified. 2. based on measurements on bench with 32. 768 khz external cr ystal oscillator. 3. rtc clock is lse divided by 32. table 23. total current consumption and timing in halt mode at v dd = 1.8 to 3.6 v symbol parameter condition (1) typ max unit i dd(halt) supply current in halt mode (ultra-low-power ulp bit =1 in the pwr_csr2 register ) t a = -40 c to 25 c 350 1400 (2) na t a = 55 c 580 2000 t a = 85 c 1160 2800 (2) i dd(wuhalt) supply current during wakeup time from halt mode (using hsi) 2.4 ma t wu_hsi(halt) (3)(4) wakeup time from halt to run mode (using hsi) 4.7 7 s t wu_lsi(halt) (3)(4) wakeup time from halt mode to run mode (using lsi) 150 s 1. t a = -40 to 85 c, no floating i/o , unless otherwise specified. 2. tested in production. 3. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register. 4. wakeup time until start of interrupt vector fetch. the first word of interrupt routi ne is fetched 4 cpu cycles after t wu . electrical parameters stm8l052c6 66/102 doc id 023331 rev 1 current consumption of on-chip peripherals table 24. peripheral current consumption symbol parameter typ. v dd = 3.0 v unit i dd(tim1) tim1 supply current (1) 13 a/mhz i dd(tim2) tim2 supply current (1) 8 i dd(tim3) tim3 supply current (1) 8 i dd(tim4) tim4 timer supply current (1) 3 i dd(usart1) usart1 supply current (2) 6 i dd(spi1) spi1 supply current (2) 3 i dd(i2c1) i 2 c1 supply current (2) 5 i dd(dma1) dma1 supply current (2) 3 i dd(wwdg) wwdg supply current (2) 2 i dd(all) peripherals on (3) 44 a/mhz i dd(adc1) adc1 supply current (4) 1500 a i dd(pvd/bor) power voltage detector and brownout reset unit supply current (5) 2.6 i dd(bor) brownout reset unit supply current (5) 2.4 i dd(idwdg) independent watchdog supply current including lsi supply current 0.45 excluding lsi supply current 0.05 1. data based on a differential i dd measurement between all peripherals off an d a timer counter running at 16 mhz. the cpu is in wait mode in both cases. no ic/oc progr ammed, no i/o pins toggling. not tested in production. 2. data based on a differential i dd measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. the cpu is in wait mode in both cases. no i/o pins toggling. not tested in production. 3. peripherals listed above the i dd(all) parameter on: tim1, tim2, tim3, tim4, usart1, spi1, i2c1, dma1, wwdg. 4. data based on a differential i dd measurement between adc in reset conf iguration and contin uous adc conversion. 5. including supply current of internal reference voltage. table 25. current consumption under external reset symbol parameter conditions typ unit i dd(rst) supply current under external reset (1) all pins are externally tied to v dd v dd = 1.8 v 48 a v dd = 3 v 76 v dd = 3.6 v 91 1. all pins except pa0, pb0 and pb4 are floating under rese t. pa0, pb0 and pb4 are confi gured with pull-up under reset. stm8l052c6 electrical parameters doc id 023331 rev 1 67/102 8.3.4 clock and timi ng characteristics hse external clock (hsebyp = 1 in clk_eckcr) subject to general operating conditions for v dd and t a . lse external clock (lsebyp=1 in clk_eckcr) subject to general operating conditions for v dd and t a . table 26. hse external clock characteristics symbol parameter conditions min typ max unit f hse_ext external clock source frequency (1) 1. data guaranteed by design, not tested in production. 116mhz v hseh osc_in input pin high level voltage 0.7 x v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3 x v dd c in(hse) osc_in input capacitance (1) 2.6 pf i leak_hse osc_in input leakage current v ss < v in < v dd 1 a table 27. lse external clock characteristics symbol parameter min typ max unit f lse_ext external clock source frequency (1) 32.768 khz v lseh (2) osc32_in input pin high level voltage 0.7 x v dd v dd v v lsel (2) osc32_in input pin low level voltage v ss 0.3 x v dd c in(lse) osc32_in input capacitance (1) 0.6 pf i leak_lse osc32_in input leakage current 1 a 1. data guaranteed by design, not tested in production. 2. data based on characterization results, not tested in production. electrical parameters stm8l052c6 68/102 doc id 023331 rev 1 hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). figure 12. hse oscillator circuit diagram hse oscillator critical g m formula r m : motional resistance (see crystal specification), l m : motional inductance (see crystal specification), c m : motional capacitance (see crystal specification), co: shunt capacitance (see crystal specification), c l1 =c l2 =c: grounded external capacitance g m >> g mcrit table 28. hse oscillator characteristics symbol parameter conditions min typ max unit f hse high speed external oscillator frequency 116mhz r f feedback resistor 200 k c (1) recommended load capacitance (2) 20 pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 16 mhz 2.5 (startup) 0.7 (stabilized) (3) ma c = 10 pf, f osc =16 mhz 2.5 (startup) 0.46 (stabilized) (3) g m oscillator transconductance 3.5 (3) ma/v t su(hse) (4) startup time v dd is stabilized 1 ms 1. c= c l1 = c l2 is approximately equiva lent to 2 x crystal c load . 2. the oscillator selection can be optimized in terms of supply current using a high qual ity resonator with small r m value. refer to crystal manufacturer for more details 3. data guaranteed by design. not tested in production. 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabili zed 16 mhz oscillation. this value is measured for a standar d crystal resonator and it can vary signi ficantly with the crystal manufacturer. osc_out osc_in f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator g mcrit 2 f hse () 2 r m 2co c + () 2 = stm8l052c6 electrical parameters doc id 023331 rev 1 69/102 lse crystal/ceramic resonator oscillator the lse clock can be supplied with a 32.768 kh z crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). figure 13. lse oscillator circuit diagram table 29. lse oscillator characteristics symbol parameter conditions min typ max unit f lse low speed external oscillator frequency 32.768 khz r f feedback resistor v = 200 mv 1.2 m c (1) recommended load capacitance (2) 8pf i dd(lse) lse oscillator power consumption 1.4 (3) a v dd = 1.8 v 450 na v dd = 3 v 600 v dd = 3.6 v 750 g m oscillator transconductance 3 (3) a/v t su(lse) (4) startup time v dd is stabilized 1 s 1. c= c l1 = c l2 is approximately equiva lent to 2 x crystal c load . 2. the oscillator selection can be optimized in terms of s upply current using a high qualit y resonator with a small r m value. refer to crystal manufacturer for more details. 3. data guaranteed by design. not tested in production. 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabi lized 32.768 khz oscillation. this value is measured for a standard crys tal resonator and it can vary signific antly with the crystal manufacturer. osc_out osc_in f lse c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator electrical parameters stm8l052c6 70/102 doc id 023331 rev 1 internal clock sources subject to general operating conditions for v dd , and t a . high speed internal rc oscillator (hsi) in the following table, data is based on characterization results, not tested in production, unless otherwise specified. figure 14. typical hsi frequency vs v dd table 30. hsi oscillator characteristics symbol parameter conditions (1) min typ max unit f hsi frequency v dd = 3.0 v 16 mhz acc hsi accuracy of hsi oscillator (factory calibrated) v dd = 3.0 v, t a = 25 c -1 (2) 1 (2) % 1.8 v v dd 3.6 v, -40 c t a 85 c -5 5 % trim hsi user trimming step (3) trimming code multiple of 16 0.4 0.7 % trimming code = multiple of 16 1.5 % t su(hsi) hsi oscillator setup time (wakeup time) 3.7 6 (4) s i dd(hsi) hsi oscillator power consumption 100 140 (4) a 1. v dd = 3.0 v, t a = -40 to 85 c unless otherwise specified. 2. tested in production. 3. the trimming step differs depending on t he trimming code. it is usua lly negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). refer to the an3101 ?stm8l15x internal rc oscillator calib ration? application note for more details. 4. guaranteed by design, not tested in production. 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] hsi frequency [mhz] -40c 25c 85c ai18218v2 stm8l052c6 electrical parameters doc id 023331 rev 1 71/102 low speed internal rc oscillator (lsi) in the following table, data is based on characterization results, not tested in production. figure 15. typical lsi frequency vs. v dd table 31. lsi oscillator characteristics symbol parameter (1) 1. v dd = 1.8 v to 3.6 v, t a = -40 to 85 c unless otherwise specified. conditions (1) min typ max unit f lsi frequency 26 38 56 khz t su(lsi) lsi oscillator wakeup time 200 (2) 2. guaranteed by design, not tested in production. s i dd(lsi) lsi oscillator frequency drift (3) 3. this is a deviation for an individual part, once the initial frequency has been measured. 0 c t a 85 c -12 11 % 25 27 29 31 33 35 37 39 41 43 45 1.8 2.1 2.6 3.1 3.6 v dd [v] lsi frequency [khz] -40c 25c 85c ai18219v2 electrical parameters stm8l052c6 72/102 doc id 023331 rev 1 8.3.5 memory characteristics t a = -40 to 85 c unless otherwise specified. flash memory 8.3.6 i/o current inj ection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection acci dentally happens, susc eptibility tests are pe rformed on a sample basis during device characterization. table 32. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by characterization, not tested in production. halt mode (or reset) 1.8 v table 33. flash program and data eeprom memory symbol parameter conditions min typ max (1) unit v dd operating voltage (all modes, read/write/erase) f sysclk = 16 mhz 1.8 3.6 v t prog programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte) 6ms programming time for 1 to 64 bytes (block) write cycles (on erased byte) 3ms i prog programming/ erasing consumption t a = +25 c, v dd = 3.0 v 0.7 ma t a = +25 c, v dd = 1.8 v t ret (2) data retention (progr am memory) after 100 erase/write cycles at t a = ?40 to +85 c t ret = +85 c 30 (1) years data retention (data memory) after 100000 erase/write cycles at t a = ?40 to +85 c t ret = +85 c 30 (1) n rw (3) erase/write cycles (program memory) t a = ?40 to +85 c 100 (1) cycles erase/write cycles (data memory) 100 (1) (4) kcycles 1. data based on characterization results, not tested in production. 2. conforming to jedec jesd22a117 3. the physical granularity of the memory is 4 bytes, so cycl ing is performed on 4 bytes even when a write/erase operation addresses a single byte. 4. data based on characterization performed on the whole data memory. stm8l052c6 electrical parameters doc id 023331 rev 1 73/102 functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, lcd levels, etc.). the test results are give n in the following table. 8.3.7 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 34. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on true open-drain pins (pc0 and pc1) -5 +0 ma injected current on all five-volt tolerant (ft) pins -5 +0 injected current on all 3.6 v tolerant (tt) pins -5 +0 injected current on any other pin -5 +5 electrical parameters stm8l052c6 74/102 doc id 023331 rev 1 table 35. i/o static characteristics symbol parameter conditions (1) min typ max unit v il input low level voltage (2) input voltage on true open-drain pins (pc0 and pc1) v ss -0.3 0.3 x v dd v input voltage on five-volt tolerant (ft) pins (pa7 and pe0) v ss -0.3 0.3 x v dd input voltage on 3.6 v tolerant (tt) pins v ss -0.3 0.3 x v dd input voltage on any other pin v ss -0.3 0.3 x v dd v ih input high level voltage (2) input voltage on true open-drain pins (pc0 and pc1) with v dd < 2 v 0.70 x v dd 5.2 v input voltage on true open-drain pins (pc0 and pc1) with v dd 2 v 5.5 input voltage on five-volt tolerant (ft) pins (pa7 and pe0) with v dd < 2 v 0.70 x v dd 5.2 input voltage on five-volt tolerant (ft) pins (pa7 and pe0) with v dd 2 v 5.5 input voltage on 3.6 v tolerant (tt) pins 3.6 input voltage on any other pin 0.70 x v dd v dd +0.3 v hys schmitt trigger voltage hysteresis (3) i/os 200 mv true open drain i/os 200 i lkg input leakage current (4) v ss v in v dd high sink i/os --50 (5) na v ss v in v dd true open drain i/os - - 200 (5) v ss v in v dd pa0 with high sink led driver capability - - 200 (5) r pu weak pull-up equivalent resistor (2)(6) v in = v ss 30 45 60 k c io i/o pin capacitance 5 pf 1. v dd = 3.0 v, t a = -40 to 85 c unless otherwise specified. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. not tested in production. stm8l052c6 electrical parameters doc id 023331 rev 1 75/102 figure 16. typical v il and v ih vs v dd (high sink i/os) figure 17. typical v il and v ih vs v dd (true open drain i/os) 6. r pu pull-up equivalent resistor based on a resistive transistor(corresponding i pu current characteri stics described in figure 19 ). 0 0.5 1 1.5 2 2.5 3 1.8 2.1 2.6 3.1 3.6 v dd [v] v il and v ih [v] -40c 25c 85c ai18220v2 0 0.5 1 1.5 2 2.5 3 1.8 2.1 2.6 3.1 3.6 v dd [v] v il and v ih [v] -40c 25c 85c ai18221v2 electrical parameters stm8l052c6 76/102 doc id 023331 rev 1 figure 18. typical pull-up resistance r pu vs v dd with v in =v ss figure 19. typical pull-up current i pu vs v dd with v in =v ss 30 35 40 45 50 55 60 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v dd [v] pull-up resistance [k ] -40c 25c 85c ai18222v2 0 20 40 60 80 100 120 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] pull-up current [a] -40c 25c 85c ai18223v2 stm8l052c6 electrical parameters doc id 023331 rev 1 77/102 output driving current subject to general operating conditions for v dd and t a unless otherwise specified. table 36. output driving current (high sink ports) i/o type symbol parameter conditions min max unit high sink v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +2 ma, v dd = 3.0 v 0.45 v i io = +2 ma, v dd = 1.8 v 0.45 v i io = +10 ma, v dd = 3.0 v 0.7 v v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin i io = -2 ma, v dd = 3.0 v v dd -0.45 v i io = -1 ma, v dd = 1.8 v v dd -0.45 v i io = -10 ma, v dd = 3.0 v v dd -0.7 v table 37. output driving current (true open drain ports) i/o type symbol parameter conditions min max unit open drain v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +3 ma, v dd = 3.0 v 0.45 v i io = +1 ma, v dd = 1.8 v 0.45 table 38. output driving current (pa0 wi th high sink led driver capability) i/o type symbol parameter conditions min max unit ir v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 13 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +20 ma, v dd = 2.0 v 0.45 v electrical parameters stm8l052c6 78/102 doc id 023331 rev 1 figure 20. typ. v ol @ v dd = 3.0 v (high sink ports) figure 21. typ. v ol @ v dd = 1.8 v (high sink ports) 0 0.25 0.5 0.75 1 02468101214161820 i ol [ma] v ol [v] -40c 25c 85c ai18226v2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 012345678 i ol [ma] v ol [v] -40c 25c 85c ai18227v2 figure 22. typ. v ol v dd = 3.0 v (true open drain ports) figure 23. typ. v ol v dd = 1.8 v (true open drain ports) ai18228v2 0 0.1 0.2 0.3 0.4 0.5 01234567 i ol [ma] v ol [v] -40c 25c 85c 0 0.1 0.2 0.3 0.4 0.5 01234567 i ol [ma] v ol [v] -40c 25c 85c b j 7 figure 24. typ. v dd - v oh @ v dd = 3.0 v (high sink ports) figure 25. typ. v dd - v oh @ v dd = 1.8 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 2 4 6 8 101214161820 i oh [ma] v dd - v oh [v] -40c 25c 85c ai12830v2 0 0.1 0.2 0.3 0.4 0.5 01234567 i oh [ma] v dd - v oh [v] -40c 25c 85c b j 7 stm8l052c6 electrical parameters doc id 023331 rev 1 79/102 nrst pin subject to general operating conditions for v dd and t a unless otherwise specified. figure 26. typical nrst pull-up resistance r pu vs v dd table 39. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage (1) v ss 0.8 v v ih(nrst) nrst input high level voltage (1) 1.4 v dd v ol(nrst) nrst output low level voltage (1) i ol = 2 ma for 2.7 v v dd 3.6 v 0.4 i ol = 1.5 ma for v dd < 2.7 v v hyst nrst input hysteresis (3) 10%v dd (2) mv r pu(nrst) nrst pull-up equivalent resistor (1) 30 45 60 k v f(nrst) nrst input filtered pulse (3) 50 ns v nf(nrst) nrst input not filtered pulse (3) 300 1. data based on characterization results, not tested in production. 2. 200 mv min. 3. data guaranteed by design, not tested in production. 30 35 40 45 50 55 60 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 v dd [v] pull-up resistance [k ] -40c 25c 85c ai18224v2 electrical parameters stm8l052c6 80/102 doc id 023331 rev 1 figure 27. typical nrst pull-up current i pu vs v dd the reset network shown in figure 28 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il(nrst) max. level specified in ta b l e 3 9 . otherwise the reset is not taken into account internally. for power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. if the nrst signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices reset timing condit ions. the minimum recommended capacity is 10 nf. figure 28. recommended nrst pin configuration ai18225v2 0 20 40 60 80 100 120 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 v dd [v] pull-u p current [a] -40c 25 c 85 c external reset circuit stm8 filter r pu v dd internal reset nrst 0.1 f (optional) stm8l052c6 electrical parameters doc id 023331 rev 1 81/102 8.3.8 communication interfaces spi1 - serial peripheral interface unless otherwise specified, the parameters given in ta bl e 4 0 are derived from tests performed under ambient temperature, f sysclk frequency and v dd supply voltage conditions summarized in section 8.3.1 . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 40. spi1 characteristics symbol parameter conditions (1) min max unit f sck 1/t c(sck) spi1 clock frequency master mode 0 8 mhz slave mode 0 8 t r(sck) t f(sck) spi1 clock rise and fall time capacitive load: c = 30 pf - 30 ns t su(nss) (2) nss setup time slave mode 4 x 1/f sysclk - t h(nss) (2) nss hold time slave mode 80 - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f master = 8 mhz, f sck = 4 mhz 105 145 t su(mi) (2) t su(si) (2) data input setup time master mode 30 - slave mode 3 - t h(mi) (2) t h(si) (2) data input hold time master mode 15 - slave mode 0 - t a(so) (2)(3) data output access time slave mode - 3x 1/f sysclk t dis(so) (2)(4) data output disable time slave mode 30 - t v(so) (2) data output valid time slave mode (after enable edge) - 60 t v(mo) (2) data output valid time master mode (after enable edge) -20 t h(so) (2) data output hold time slave mode (after enable edge) 15 - t h(mo) (2) master mode (after enable edge) 1- 1. parameters are given by se lecting 10 mhz i/o output frequency. 2. values based on design simulation and/or charac terization results, and not tested in production. 3. min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in hi-z. electrical parameters stm8l052c6 82/102 doc id 023331 rev 1 figure 29. spi1 timing diagram - slave mode and cpha=0 figure 30. spi1 timing diagram - slave mode and cpha=1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm8l052c6 electrical parameters doc id 023331 rev 1 83/102 figure 31. spi1 timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck output cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) electrical parameters stm8l052c6 84/102 doc id 023331 rev 1 i 2 c - inter ic control interface subject to general operating conditions for v dd , f sysclk , and t a unless otherwise specified. the stm8l i 2 c interface (i2c1) meets the requirements of the standard i 2 c communication protocol described in the following table with the restriction mentioned below: refer to i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). note: for speeds around 200 khz, the achieved speed can have a 5% tolerance for other speed ranges, the achieved speed can have a 2% tolerance the above variations depend on the accuracy of the external components used. table 41. i2c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f sysclk must be at least equal to 8 mhz to achieve max fast i 2 c speed (400 khz). unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production. max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 0 900 t r(sda) t r(scl) sda and scl rise time 1000 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf stm8l052c6 electrical parameters doc id 023331 rev 1 85/102 figure 32. typical application with i 2 c bus and timing diagram 1) 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(scl) t r(scl) t w(scll) t w(sclh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda scl 4.7k sda stm8l scl v dd 100 100 v dd 4.7k i 2 cbus electrical parameters stm8l052c6 86/102 doc id 023331 rev 1 8.3.9 lcd controller in the following table, data is guaranteed by design. not tested in production. vlcd external capacitor the application can achieve a stabilized lcd reference voltage by connecting an external capacitor c ext to the v lcd pin. c ext is specified in ta bl e 4 2 . table 42. lcd characteristics symbol parameter min typ max. unit v lcd lcd external voltage 3.6 v v lcd0 lcd internal reference voltage 0 2.6 v v lcd1 lcd internal reference voltage 1 2.7 v v lcd2 lcd internal reference voltage 2 2.8 v v lcd3 lcd internal reference voltage 3 2.9 v v lcd4 lcd internal reference voltage 4 3.0 v v lcd5 lcd internal reference voltage 5 3.1 v v lcd6 lcd internal reference voltage 6 3.2 v v lcd7 lcd internal reference voltage 7 3.3 v c ext v lcd external capacitance 0.1 2 f i dd supply current (1) at v dd = 1.8 v 1. lcd enabled with 3 v internal booster (lcd_cr1 = 0x08), 1/ 4 duty, 1/3 bias, division ratio= 64, all pixels active, no lcd connected. 3a supply current (1) at v dd = 3 v 3 a r hn (2) 2. r hn is the total high value resistive network. high value resistive network (low drive) 6.6 m r ln (3) 3. r ln is the total low value resistive network. low value resistive network (high drive) 360 k v 33 segment/common higher level voltage v lcdx v v 23 segment/common 2/3 level voltage 2/3v lcdx v v 12 segment/common 1/2 level voltage 1/2v lcdx v v 13 segment/common 1/3 level voltage 1/3v lcdx v v 0 segment/common lowest level voltage 0 v stm8l052c6 electrical parameters doc id 023331 rev 1 87/102 8.3.10 embedded reference voltage in the following table, data is based on characterization results, not tested in production, unless otherwise specified. table 43. reference voltage characteristics symbol parameter conditions min typ max. unit i refint internal reference voltage consumption 1.4 a t s_vrefint (1)(2) adc sampling time when reading the internal reference voltage 510 s i buf (2) internal reference voltage buffer consumption (used for adc) 13.5 25 a v refint out reference voltage output 1.202 (3) 1.224 1.242 (3) v i lpbuf (2) internal reference voltage low power buffer consumption 730 1200 na i refout (2) buffer output current (4) 1a c refout reference voltage output load 50 pf t vrefint internal reference voltage startup time 23ms t bufen (2) internal reference voltage buffer startup time once enabled (1) 10 s acc vrefint accuracy of v refint stored in the vrefint_factory_conv byte (5) 5 mv stab vrefint stability of v refint over temperature -40 c t a 85 c 20 50 ppm/c stability of v refint over temperature 0 c t a 50 c 20 ppm/c stab vrefint stability of v refint after 1000 hours tbd ppm 1. defined when adc output reaches its final value 1/2lsb 2. data guaranteed by design. not tested in production. 3. tested in production at v dd = 3 v 10 mv. 4. to guaranty less than 1% v refout deviation. 5. measured at v dd = 3 v 10 mv. this value takes into account v dd accuracy and adc conversion accuracy. electrical parameters stm8l052c6 88/102 doc id 023331 rev 1 8.3.11 12-bit adc1 characteristics in the following table, data is guaranteed by design, not tested in production. table 44. adc1 characteristics symbol parameter conditions min typ max unit v dda analog supply voltage 1.8 3.6 v v ref+ reference supply voltage 2.4 v v dda 3.6 v 2.4 v dda v 1.8 v v dda 2.4 v v dda v v ref- lower reference voltage v ssa v i vdda current on the v dda input pin 1000 1450 a i vref+ current on the v ref+ input pin 400 700 (peak) (1) a 450 (average) (1) a v ain conversion voltage range 0 (2) v ref+ t a temperature range -40 85 c r ain external resistance on v ain on pf0 fast channel 50 (3) k on all other channels c adc internal sample and hold capacitor on pf0 fast channel 16 pf on all other channels f adc adc sampling clock frequency 2.4 v v dda 3.6 v without zooming 0.320 16 mhz 1.8 v v dda 2.4 v with zooming 0.320 8 mhz f conv 12-bit conversion rate v ain on pf0 fast channel 1 (4)(5) mhz v ain on all other channels 760 (4)(5) khz f trig external trigger frequency t conv 1/f adc t lat external trigger latency 3.5 1/f sysclk stm8l052c6 electrical parameters doc id 023331 rev 1 89/102 t s sampling time v ain on pf0 fast channel v dda < 2.4 v 0.43 (4)(5) s v ain on pf0 fast channel 2.4 v v dda 3.6 v 0.22 (4)(5) s v ain on slow channels v dda < 2.4 v 0.86 (4)(5) s v ain on slow channels 2.4 v v dda 3.6 v 0.41 (4)(5) s t conv 12-bit conversion time 12 + t s 1/f adc 16 mhz 1 (4) s t wkup wakeup time from off state 3s t idle (6) time before a new conversion t a = +25 c 1 (7) s t a = +70 c 20 (7) ms t vrefint internal reference voltage startup time refer to ta bl e 4 3 ms 1. the current consumption through v ref is composed of two parameters: - one constant (max 300 a) - one variable (max 400 a), only during sa mpling time + 2 first conversion pulses. so, peak consumption is 300+400 = 700 a and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 a at 1msps 2. v ref- or v dda must be tied to ground. 3. guaranteed by design, not tested in production. 4. minimum sampling and conversion time is reached for maximum rext = 0.5 k . 5. value obtained for continuous conversion on fast channel. 6. the time between 2 conversions, or between adc on and the first conversion must be lower than t idle. 7. the t idle maximum value is on the ?z? revision code of the device. table 44. adc1 character istics (continued) symbol parameter conditions min typ max unit electrical parameters stm8l052c6 90/102 doc id 023331 rev 1 in the following three tables, data is guaranteed by characterization result, not tested in production. table 45. adc1 accuracy with v dda = 3.3 v to 2.5 v symbol parameter conditions typ max unit dnl differential non linearity f adc = 16 mhz 1 1.6 lsb f adc = 8 mhz 1 1.6 f adc = 4 mhz 1 1.5 inl integral non linearity f adc = 16 mhz 1.2 2 f adc = 8 mhz 1.2 1.8 f adc = 4 mhz 1.2 1.7 tue total unadjusted error f adc = 16 mhz 2.2 3.0 f adc = 8 mhz 1.8 2.5 f adc = 4 mhz 1.8 2.3 offset offset error f adc = 16 mhz 1.5 2 lsb f adc = 8 mhz 1 1.5 f adc = 4 mhz 0.7 1.2 gain gain error f adc = 16 mhz 11.5 f adc = 8 mhz f adc = 4 mhz table 46. adc1 accuracy with v dda = 2.4 v to 3.6 v symbol parameter typ max unit dnl differential non linearity 1 2 lsb inl integral non linearity 1.7 3 lsb tue total unadjusted error 24lsb offset offset error 1 2 lsb gain gain error 1.5 3 lsb table 47. adc1 accuracy with v dda = v ref+ = 1.8 v to 2.4 v symbol parameter typ max unit dnl differential non linearity 1 2 lsb inl integral non linearity 23lsb tue total unadjusted error 35lsb offset offset error 2 3 lsb gain gain error 2 3 lsb stm8l052c6 electrical parameters doc id 023331 rev 1 91/102 figure 33. adc1 accuracy characteristics figure 34. typical connection diagram using the adc 1. refer to ta b l e 4 4 for the values of r ain and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = ai17090e stm8l05xxx v dd ainx i l 50 na 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc c adc (1) 12-bit converter sample and hold adc converter electrical parameters stm8l052c6 92/102 doc id 023331 rev 1 figure 35. maximum dynamic current consumption on v ref+ supply pin during adc conversion general pcb design guidelines power supply decoupling should be performed as shown in figure 36 or figure 37 , depending on whether v ref+ is connected to v dda or not. good quality ceramic 10 nf capacitors should be used. they should be placed as close as possible to the chip. adc clock sampling (n cycles) conversion (12 cycles) i ref+ 300a 700a table 48. r ain max for f adc = 16 mhz (1) ts (cycles) ts (s) r ain max (kohm) slow channels fast channels 2.4 v < v dda < 3.6 v 1.8 v < v dda < 2.4 v 2.4 v < v dda < 3.3 v 1.8 v < v dda < 2.4 v 4 0.25 not allowed not allowed 0.7 not allowed 9 0.5625 0.8 not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. guaranteed by design, not tested in production. stm8l052c6 electrical parameters doc id 023331 rev 1 93/102 figure 36. power supply and reference decoupling (v ref+ not connected to v dda ) figure 37. power supply and reference decoupling (v ref+ connected to v dda ) v ref+ s tm8l stm8l v dda v ssa /v ref- 1 f // 10 nf 1 f // 10 n f 1 f // 10 nf supply external reference ai17031b v ref+ /v dda stm8l 1 f // 10 nf v refC /v ssa ai17032b supply electrical parameters stm8l052c6 94/102 doc id 023331 rev 1 8.3.12 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electromagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm iec61967-2 which specifies the board and the loading of each pin. table 49. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 using hsi 4a using hse 2b stm8l052c6 electrical parameters doc id 023331 rev 1 95/102 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and charge device model. this test conforms to the jesd22-a114a/a115a standard. static latch-up lu : 3 complementary static tests are required on 6 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 50. emi data (1) 1. not tested in production. symbol parameter conditions monitored frequency band max vs. unit 16 mhz s emi peak level v dd = 3.6 v, t a = +25 c, lqfp32 conforming to iec61967-2 0.1 mhz to 30 mhz -3 db v 30 mhz to 130 mhz 9 130 mhz to 1 ghz 4 sae emi level 2 - table 51. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) 500 table 52. electrical sensitivities symbol parameter class lu static latch-up class ii electrical parameters stm8l052c6 96/102 doc id 023331 rev 1 8.4 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 15: general operating conditions on page 55 . the maximum chip-junction temperature, t jmax , in degree celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 53. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 48- 7 x 7 mm 65 c/w stm8l052c6 package characteristics doc id 023331 rev 1 97/102 9 package characteristics 9.1 ecopack in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. package characteristics stm8l052c6 98/102 doc id 023331 rev 1 9.2 package mechanical data 9.2.1 48-pin low profile qu ad flat 7x7mm package (lqfp48) figure 38. lqfp48 48-pin low profile quad flat package outline 1. drawing is not to scale. table 54. lqfp48 48-pin low profile quad flat package, mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.6 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.2 0.0035 0.0079 d 8.8 9 9.2 0.3465 0.3543 0.3622 d1 6.8 7 7.2 0.2677 0.2756 0.2835 d3 5.5 0.2165 e 8.8 9 9.2 0.3465 0.3543 0.3622 e1 6.8 7 7.2 0.2677 0.2756 0.2835 e3 5.5 0.2165 e 0.5 0.0197 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.08 0.0031 5b_me l a1 k l1 d " " ccc $ d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 stm8l052c6 package characteristics doc id 023331 rev 1 99/102 figure 39. lqfp48 recommended footprint 1. dimensions are in millimeters. 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 5b_fp 13 48 device ordering information stm8l052c6 100/102 doc id 023331 rev 1 10 device ordering information figure 40. medium density value line stm8l05xxx ordering information scheme 1. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please contact the st sales office nearest to you stm8 l 052 c 6 t 6 product class stm8 microcontroller pin count c = 48 pins example: sub-family type 052 = ultra-low-power with lcd family type l = low power temperature range 6 = - 40 c to 85 c program memory size 6 = 32 kbytes package t = lqfp stm8l052c6 revision history doc id 023331 rev 1 101/102 11 revision history table 55. document revision history date revision changes 22-jun-2012 1 initial release. stm8l052c6 102/102 doc id 023331 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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